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XRT86SH328IB Datasheet(PDF) 6 Page - Exar Corporation |
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XRT86SH328IB Datasheet(HTML) 6 Page - Exar Corporation |
6 / 159 page XRT86SH328 I SONET TO 28-T1/21-E1 PDH MAPPER - VOYAGER PIN AND ARCHITECTURE DESC REV. 1.0.1 TABLE OF CONTENTS GENERAL DESCRIPTION ................................................................................................ 1 FIGURE 1. SIMPLIFIED BLOCK DIAGRAM ............................................................................................................................................ 1 PACKAGE ORDERING INFORMATION ...................................................................................................... 2 FEATURES ........................................................................................................................ 3 TABLE OF CONTENTS...................................................................................................... I 1.0 PIN DESCRIPTIONS ................................................................................................................................ 6 1.1 MICROPROCESSOR INTERFACE PINS............................................................................................................ 6 1.2 BOUNDARY SCAN AND OTHER TEST PINS.................................................................................................... 9 1.3 GENERAL PURPOSE INPUT AND OUTPUT PINS.......................................................................................... 10 1.4 TIMING AND CLOCK SIGNALS........................................................................................................................ 10 1.5 LOW SPEED LINE INTERFACE SIGNALS ...................................................................................................... 13 1.6 HIGH SPEED SERIAL INTERFACE.................................................................................................................. 17 1.7 HIGH SPEED TELECOM BUS INTERFACE.................................................................................................... 18 1.8 HIGH SPEED SECTION AND PATH OVERHEAD BUS ................................................................................... 20 1.9 HIGH SPEED TU POH OVERHEAD BUS ......................................................................................................... 21 1.10 FRAMER + LIU COMBO MODE ...................................................................................................................... 23 1.11 POWER AND GROUND PINS ......................................................................................................................... 29 2.0 APPLICATIONS AND PHYSICAL INTERFACE GENERAL OVERVIEW............................................. 30 FIGURE 1. APPLICATION DIAGRAM .................................................................................................................................................. 31 2.1 PHYSICAL INTERFACE .................................................................................................................................... 31 FIGURE 2. SIMPLIFIED BLOCK DIAGRAM OF THE PHYSICAL INTERFACE ............................................................................................. 32 2.2 TELECOM BUS INTERFACE ............................................................................................................................ 33 FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE TELECOM BUS INTERFACE ...................................................................................... 33 2.3 STS1 SERIAL INTERFACE SONET FRAME SYNCHRONIZATION AND TIMING INTERFACE .................... 34 FIGURE 4. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL PORT INTERFACE ....................................................................................... 34 2.4 SONET FRAME SYNCHRONIZATION AND TIMING INTERFACE.................................................................. 35 FIGURE 5. SIMPLIFIED BLOCK DIAGRAM OF THE SONET FRAME SYNCHRONIZATION ........................................................................ 35 2.5 SONET OVERHEAD ADD-DROP INTERFACES.............................................................................................. 36 FIGURE 6. SIMPLIFIED BLOCK DIAGRAM OF THE SONET OVERHEAD ADD-DROP INTERFACE ............................................................ 36 2.6 T1/E1 SHORT HAUL LINE INTERFACE........................................................................................................... 37 2.7 T1/E1 TIMING INTERFACE ............................................................................................................................... 38 2.8 MICROPROCESSOR INTERFACE ................................................................................................................... 38 3.0 FUNCTIONAL DESCRIPTION ............................................................................................................... 39 FIGURE 7. FUNCTIONAL BLOCK DIAGRAM........................................................................................................................................ 39 3.1 INGRESS DATA PATH FUNCTIONAL BLOCKS ............................................................................................. 40 FIGURE 8. SIMPLIFIED BLOCK DIAGRAM OF THE INGRESS DATA PATH.............................................................................................. 40 3.2 T1/E1 RECEIVE LIU (RXT1/E1LIU)................................................................................................................... 40 3.3 TRANSMIT VIRTUAL CIRCUIT - 4 POH OVERHEAD INSERTION BUS (TXTUPOH).................................... 40 3.4 VT1.5/VT2 TRANSMIT VT-POH MAPPER AND OVERHEAD PROCESSOR (TXVTPOHPROC) ................... 41 3.5 VT1.5/VT2 TRANSMIT CROSS-CONNECT (TXVT1.5/VT2XC) ........................................................................ 41 3.6 TRANSMIT SONET TOH/POH INSERTION BUS (TXTPOH) ........................................................................... 41 3.7 SONET TRANSMIT MAPPER AND PATH OVERHEAD PROCESSOR (TXPOHPROC) ................................ 42 3.8 SONET TRANSMIT FRAMER AND TRANSPORT OVERHEAD PROCESSOR (TXTOHPROC) .................... 43 3.9 TRANSMIT TELECOM BUS (TXTBUS) ............................................................................................................ 44 3.10 EGRESS DATA PATH FUNCTIONAL BLOCKS ............................................................................................ 45 FIGURE 9. SIMPLIFIED BLOCK DIAGRAM OF THE EGRESS DATA PATH .............................................................................................. 45 3.11 RECEIVE TELECOM BUS (RXTBUS)............................................................................................................. 45 3.12 SONET RECEIVE FRAMER AND TRANSPORT OVERHEAD PROCESSOR (RXTOHPROC) .................... 46 3.13 SONET RECEIVE MAPPER AND PATH OVERHEAD PROCESSOR (RXPOHPROC)................................. 47 4.0 VOYAGER HARDWARE ARCHITECTURE AND ALGORITHMS ........................................................ 48 FIGURE 10. VOYAGER ARCHITECTURE ............................................................................................................................................ 48 4.1 MULTIPLEXING STRUCTURE.......................................................................................................................... 49 FIGURE 11. VOYAGER SONET MULTIPLEXING STRUCTURE ............................................................................................................ 49 FIGURE 12. VOYAGER SDH MULTIPLEXING STRUCTURE.................................................................................................................. 49 4.2 FUNCTIONAL BLOCKS .................................................................................................................................... 50 4.3 SONET TRANSMIT DATA FLOW ..................................................................................................................... 50 FIGURE 13. SONET TRANSMITTER GENERAL STRUCTURE.............................................................................................................. 51 4.4 SONET RECEIVE DATA FLOW ........................................................................................................................ 51 |
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