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XRT86SH328IB Datasheet(PDF) 8 Page - Exar Corporation |
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XRT86SH328IB Datasheet(HTML) 8 Page - Exar Corporation |
8 / 159 page XRT86SH328 III SONET TO 28-T1/21-E1 PDH MAPPER - VOYAGER PIN AND ARCHITECTURE DESC REV. 1.0.1 5.1.1 JITTER ATTENUATOR ............................................................................................................................................... 109 5.1.2 TAOS (TRANSMIT ALL ONES).................................................................................................................................. 109 FIGURE 47. TAOS (TRANSMIT ALL ONES) .................................................................................................................................... 109 5.1.3 ATAOS (AUTOMATIC TRANSMIT ALL ONES)......................................................................................................... 109 FIGURE 48. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION............................................................................................. 109 5.1.4 QRSS/PRBS GENERATION....................................................................................................................................... 110 5.1.5 TRANSMIT PULSE SHAPER AND FILTER ............................................................................................................... 110 5.1.6 DMO (DIGITAL MONITOR OUTPUT) ......................................................................................................................... 110 5.2 LINE TERMINATION (TTIP/TRING) ................................................................................................................ 110 FIGURE 49. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION ................................................................................. 110 5.3 RECEIVE PATH LINE INTERFACE ................................................................................................................ 111 FIGURE 50. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH .................................................................................................. 111 5.3.1 LINE TERMINATION (RTIP/RRING)........................................................................................................................... 111 FIGURE 51. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION ................................................................................ 111 5.3.2 CLOCK AND DATA RECOVERY .............................................................................................................................. 112 FIGURE 52. RECOVERED LINE CLOCK PLL TIMING........................................................................................................................ 112 5.3.3 RECOVERED LINE CLOCK OUTPUTS ..................................................................................................................... 112 FIGURE 53. REF_REC[1:0] RECOVERED LINE CLOCK SELECTION TO OUTPUT PINS ..................................................................... 112 5.3.4 RLOS (RECEIVER LOSS OF SIGNAL)...................................................................................................................... 113 5.3.5 EXLOS (EXTENDED LOSS OF SIGNAL) .................................................................................................................. 113 5.3.6 JITTER ATTENUATOR ............................................................................................................................................... 113 5.3.7 RXMUTE (RECEIVER LOS WITH DATA MUTING) ................................................................................................... 113 FIGURE 54. SIMPLIFIED BLOCK DIAGRAM OF THE RXMUTE FUNCTION .......................................................................................... 113 6.0 MICROPROCESSOR INTERFACE TIMING ........................................................................................ 114 6.1 MICROPROCESSOR INTERFACE TIMING - INTEL ASYNCHRONOUS MODE .......................................... 114 FIGURE 55. INTEL-ASYNCHRONOUS MODE TIMING - WRITE OPERATION......................................................................................... 114 TABLE 15 INTEL ASYNCHRONOUS MODE TIMING - WRITE OPERATION ........................................................................................... 115 FIGURE 56. INTEL-ASYNCHRONOUS MODE TIMING - READ OPERATION .......................................................................................... 115 TABLE 16 INTEL ASYNCHRONOUS MODE TIMING - READ OPERATION ............................................................................................. 115 6.2 MICROPROCESSOR INTERFACE TIMING - MOTOROLA ASYNCHRONOUS (68K) MODE...................... 116 FIGURE 57. MOTOROLA-ASYNCHRONOUS MODE TIMING - WRITE OPERATION................................................................................ 116 TABLE 17 MOTOROLA (68K) ASYNCHRONOUS MODE TIMING INFORMATION - WRITE OPERATION .................................................... 116 6.2.1 MOTOROLA-ASYNCHRONOUS MODE TIMING - READ OPERATION.................................................................. 117 FIGURE 58. MOTOROLA-ASYNCHRONOUS MODE TIMING - READ OPERATION ................................................................................. 117 TABLE 18 MOTOROLA (68K) ASYNCHRONOUS MODE TIMING - READ OPERATION .......................................................................... 117 6.3 POWERPC 403 SYNCHRONOUS MODE:...................................................................................................... 118 FIGURE 59. POWERPC 403 MODE TIMING - WRITE OPERATION .................................................................................................... 118 TABLE 19 POWER PC403 MODE TIMING - WRITE OPERATION ....................................................................................................... 118 FIGURE 60. POWERPC 403 MODE TIMING - READ OPERATION ..................................................................................................... 119 TABLE 20 POWER PC403 MODE TIMING - READ OPERATION ........................................................................................................ 119 6.4 MICROPROCESSOR INTERFACE TIMING - MCP860 SYNCHRONOUS MODE ......................................... 120 FIGURE 61. MPC86X MODE TIMING - WRITE OPERATION............................................................................................................. 120 TABLE 21 MPC86X MODE TIMING - WRITE OPERATION ................................................................................................................ 120 TABLE 22 MPC86X TIMING INFORMATION - READ OPERATION ...................................................................................................... 121 FIGURE 62. MPC86X MODE TIMING - READ OPERATION .............................................................................................................. 121 7.0 INTERFACE TIMING SPECIFICATIONS............................................................................................. 122 7.1 STS1/STS3 TELECOM BUS INTERFACE TIMING INFORMATION .............................................................. 122 7.2 THE TRANSMIT STS1/STS3 TELECOM BUS INTERFACE TIMING - STS1 APPLICATIONS..................... 122 FIGURE 63. AN ILLUSTRATION OF THE WAVEFORMS OF THE SIGNALS THAT ARE OUTPUT VIA THE TRANSMIT STS1/STS3 TELECOM BUS IN- TERFACE (FOR STS1 APPLICATIONS) ........................................................................................................................... 122 TABLE 23 TIMING INFORMATION FOR THE TRANSMIT STS1 TELECOM BUS INTERFACE - STS1 APPLICATIONS ................................. 123 7.3 THE TRANSMIT STS1/STS3 TELECOM BUS INTERFACE TIMING - STS3 SLOT MASTER APPLICATIONS. 123 FIGURE 64. AN ILLUSTRATION OF THE WAVEFORMS OF THE SIGNALS THAT ARE OUTPUT VIA THE TRANSMIT STS1/STS3 TELECOM BUS IN- TERFACE (FOR STS3 APPLICATIONS) ........................................................................................................................... 123 FIGURE 65. AN ILLUSTRATION OF THE TIMING RELATIONSHIPS BETWEEN THE TXSBFP_IN_OUT OUTPUT PIN, AND THE TXA_CLK OUTPUT PIN , WITHIN THE TRANSMIT STS3 TELECOM BUS INTERFACE (SLOT MASTER MODE APPLICATION)................................. 124 TABLE 24 TIMING INFORMATION FOR THE TRANSMIT STS1/STS3 TELECOM BUS INTERFACE - STS3 SLOT MASTER APPLICATIONS 124 7.4 THE TRANSMIT STS1/STS3 TELECOM BUS INTERFACE TIMING - STS3 SLOT SLAVE APPLICATIONS 125 FIGURE 66. AN ILLUSTRATION OF THE WAVEFORMS OF THE SIGNALS THAT ARE OUTPUT VIA THE TRANSMIT STS1/STS3 TELECOM BUS IN- TERFACE (FOR STS3 APPLICATIONS) ........................................................................................................................... 125 FIGURE 67. AN ILLUSTRATION OF THE TIMING RELATIONSHIPS BETWEEN THE TXSBFP INPUT PIN AND THE TXA_CLK OUTPUT PIN WITHIN THE TRANSMIT STS1/STS3 TELECOM BUS INTERFACE (STS3 SLOT SLAVE APPLICATIONS)................................................. 125 TABLE 25 TIMING INFORMATION FOR THE TRANSMIT STS1/STS3 TELECOM BUS INTERFACE - STS3 SLOT SLAVE APPLICATIONS ... 126 7.5 THE RECEIVE STS1/STS3 TELECOM BUS INTERFACE TIMING - STS1 APPLICATIONS ....................... 126 |
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