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XRT86SH328 Datasheet(PDF) 7 Page - Exar Corporation |
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XRT86SH328 Datasheet(HTML) 7 Page - Exar Corporation |
7 / 159 page XRT86SH328 II REV. 1.0.1 SONET TO 28-T1/21-E1 PDH MAPPER - VOYAGER PIN AND ARCHITECTURE DESC FIGURE 14. GENERAL COMPOSITION OF A SONET STS-N RECEIVER............................................................................................. 52 4.5 VT MAPPER ..................................................................................................................................................... 52 FIGURE 15. TOP LEVEL BLOCK DIAGRAM........................................................................................................................................ 53 4.6 INTERRUPTS AND STATUS ............................................................................................................................ 54 FIGURE 16. INTERRUPT HIERARCHY ............................................................................................................................................... 54 4.7 INTERRUPT PROCESSING AND CONTROL .................................................................................................. 55 4.8 STS1/STS3 RECEIVE TRANSPORT PROCESSOR ........................................................................................ 55 FIGURE 17. BYTE_ALIGN BLOCK FUNCTIONAL DIAGRAM .............................................................................................................. 55 TABLE 1: 16-BYTE FRAME FOR TRAIL APID ..................................................................................................................................... 60 FIGURE 18. RECEIVE TRACE BUFFER MEMORY............................................................................................................................... 61 TABLE 2: ADDRESSING SCHEME USED TO ACCESS THE SONET OH BYTES .................................................................................... 62 FIGURE 19. RECEIVE TRANSPORT OVERHEAD INTERFACE TIMING ................................................................................................... 63 STS1/STS3 RECEIVE PATH PROCESSOR ........................................................................................... 64 FIGURE 20. POINTER PROCESSING FSM ........................................................................................................................................ 66 TABLE 3: SONET POINTER EVENT TYPES ...................................................................................................................................... 66 FIGURE 21. CONCATENATED POINTER INDICATOR PROCESSING FSM.............................................................................................. 68 TABLE 4: RDI-P SETTINGS AND INTERPRETATION ........................................................................................................................... 69 TABLE 5: STS SIGNAL LABEL MISMATCH DEFECT CONDITIONS ....................................................................................................... 70 TABLE 6: TRUTH TABLE FOR PATH LABEL ERROR CONDITIONS ....................................................................................................... 70 FIGURE 22. PATH OVERHEAD INTERFACE TIMING............................................................................................................................ 73 FIGURE 23. TRANSMIT TRANSPORT OVERHEAD INTERFACE TIMING ................................................................................................. 74 4.9 TELECOM BUS INTERFACE............................................................................................................................ 79 4.9.1 TRANSMIT TELECOM BUS ......................................................................................................................................... 79 FIGURE 24. TRANSMIT TELECOM BUS INTERFACE TIMING................................................................................................................ 79 4.9.2 2KHZ MODE IN STS3 ................................................................................................................................................... 80 FIGURE 25. C1J1V1 PULSE IN STS3 2KHZ MODE ......................................................................................................................... 80 4.9.3 RECEIVE TELECOM BUS ............................................................................................................................................ 80 FIGURE 26. RECEIVE TELECOM BUS INTERFACE TIMING.................................................................................................................. 80 4.10 VT MAPPER .................................................................................................................................................... 81 FIGURE 27. INTERNAL BUS STRUCTURE ......................................................................................................................................... 81 FIGURE 28. MID BUS INTERFACE.................................................................................................................................................... 83 FIGURE 29. SONET TO VTM DATA TRANSFER WITH ZERO POINTER OFFSET.................................................................................... 83 FIGURE 30. VTM TO SONET DATA TRANSFER ............................................................................................................................... 84 FIGURE 31. T1/E1 INTERFACE TIMING (INTERNAL TO THE CHIP) ...................................................................................................... 85 FIGURE 32. T1/E1 INTERFACE TIMING (T1/E1 SYNCHRONOUS MAPPING, INTERNAL TO THE CHIP) .................................................... 85 TABLE 7: V5 - VT PATH ERROR CHECKING, SIGNAL LABEL AND PATH STATUS ................................................................................ 86 TABLE 8: N2 BYTE STRUCTURE ...................................................................................................................................................... 88 TABLE 9: B7-B8 MULTIFRAME STRUCTURE ....................................................................................................................................... 89 TABLE 10: STRUCTURE OF FRAMES # 73 - 76 OF THE B7-B8 MULTIFRAME ....................................................................................... 89 TABLE 11: K4 (B5-B7) CODING AND INTERPRETATION ...................................................................................................................... 91 TABLE 12: Z7/K4 - VT PATH GROWTH AND VT PATH REMOTE DEFECT INDICATION ........................................................................ 91 FIGURE 33. MKP (MAKE PAYLOAD), ONE OF SEVEN MKG : MAKE VT/TU GROUP ........................................................................... 92 FIGURE 34. MKP (MAKE PAYLOAD), VT/TU GROUP INTERLEAVING................................................................................................. 93 FIGURE 35. MAKE TRIBUTARY (MKT) ............................................................................................................................................. 94 FIGURE 36. EXTRACT PAYLOAD (XTP) ........................................................................................................................................... 95 FIGURE 37. REFERENCE CLOCKS GENERATOR (RCG).................................................................................................................... 96 DATA INTERFACE BETWEEN SONET/FRAMER AND MAPPER............................................................ 97 FIGURE 38. RECEIVE SONET/FRAMER MAPPER INTERFACE ........................................................................................................... 97 FIGURE 39. TRANSMIT SONET/FRAMER MAPPER INTERFACE ......................................................................................................... 97 FIGURE 40. T1/E1 FRAMER SYNCHRONIZATION FLOW DIAGRAM ..................................................................................................... 98 FIGURE 41. FLOW OF CRC-4 MULTIFRAME ALIGNMENT FOR INTERWORKING .................................................................................. 100 4.11 T1/E1 PHY LOOPBACK DIAGNOSTICS ...................................................................................................... 103 4.11.1 T1/E1 LOOPBACKS ................................................................................................................................................. 103 FIGURE 42. T1/E1 FACILITY LOOPBACK........................................................................................................................................ 103 4.11.2 T1/E1 FACILITY I/O LOOPBACK............................................................................................................................. 104 FIGURE 43. T1/E1 FACILITY I/O LOOPBACK.................................................................................................................................. 104 4.11.3 T1/E1 MODULE LOOPBACK .................................................................................................................................. 105 FIGURE 44. T1/E1 MODULE LOOPBACK ........................................................................................................................................ 105 4.11.4 ALARM AND AUTO AIS ........................................................................................................................................... 106 FIGURE 45. T1/E1 AUTO AIS INSERTION...................................................................................................................................... 106 TABLE 13: T1/E1 TO STS1/STS3 - RESPONSE TIME < 125 USEC ................................................................................................. 106 TABLE 14: STS1/STS3 TO T1/E1 - RESPONSE TIME < 125 USEC ................................................................................................. 106 5.0 ANALOG FRONT END / LINE INTERFACE UNIT (LIU) SECTION.................................................... 108 FIGURE 46. SIMPLIFIED BLOCK DIAGRAM OF THE LIU SECTION ..................................................................................................... 108 5.1 TRANSMIT LINE INTERFACE UNIT............................................................................................................... 109 |
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