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XRT86VL32_0709 Datasheet(PDF) 6 Page - Exar Corporation |
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XRT86VL32_0709 Datasheet(HTML) 6 Page - Exar Corporation |
6 / 65 page XRT86VL32 III DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION REV. V1.2.1 LIST OF FIGURES Figure 1.: XRT86VL32 2-channel DS1 (T1/E1/J1) Framer/LIU Combo ............................................................................. 1 Figure 2.: Framer System Transmit Timing Diagram (Base Rate/Non-Mux) ................................................................... 43 Figure 3.: Framer System Receive Timing Diagram (RxSERCLK as an Output) ............................................................ 44 Figure 4.: Framer System Receive Timing Diagram (RxSERCLK as an Input) ............................................................... 45 Figure 5.: Framer System Transmit Timing Diagram (HMVIP and H100 Mode) ............................................................. 46 Figure 6.: Framer System Receive Timing Diagram (HMVIP/H100 Mode) ..................................................................... 47 Figure 7.: Framer System Transmit Overhead Timing Diagram ...................................................................................... 48 Figure 8.: Framer System Receive Overhead Timing Diagram (RxSERCLK as an Output) ........................................... 49 Figure 9.: Framer System Receive Overhead Timing Diagram (RxSERCLK as an Input) .............................................. 49 Figure 10.: ITU G.703 Pulse Template ............................................................................................................................ 54 Figure 11.: DSX-1 Pulse Template (normalized amplitude) ............................................................................................. 55 Figure 12.: Intel µP Interface Timing During Programmed I/O Read and Write Operations When ALE Is Not Tied ’HIGH’ 57 Figure 13.: Intel µP Interface Timing During Programmed I/O Read and Write Operations When ALE Is Tied ’HIGH’ .. 58 Figure 14.: Motorola Asychronous Mode Interface Signals During Programmed I/O Read and Write Operations ......... 59 Figure 15.: Power PC 403 Interface Signals During Programmed I/O Read and Write Operations ............................... 60 |
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