Electronic Components Datasheet Search |
|
XRT91L33IG Datasheet(PDF) 4 Page - Exar Corporation |
|
XRT91L33IG Datasheet(HTML) 4 Page - Exar Corporation |
4 / 16 page XRT91L33 4 STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT REV. V1.0.0 1.0 PIN DESCRIPTIONS TABLE 2: PIN DESCRIPTION TABLE NAME LEVEL TYPE PIN DESCRIPTION VDDA PWR PWR 1 3.3V Power supply RXDIP LVDS/PECL I 2 Positive side of receive data input. The high-speed output clock (RXCLKOP/N) is recovered from this high-speed differential inupt data. RXDIN LVDS/PECL I 3 Negative side of receive data input. The high-speed output clock (RXCLKOP/N) is recovered from this high-speed differen- tial input data. VSSA PWR PWR 4 Ground pin LOCK LVPECL O 5 Active HIGH to indicate that the PLL is locked to serial data input and valid clock and data are present at the serial outputs (RXDOP/N and RXCLKOP/N). The LOCK will go inactive under the following conditions: • If SIGD is set LOW • If LCKTOREFN is set LOW • If the VCO has drifted away from the local reference clock, REFCK, by more than +/- 500 ppm STS12_MODE LVTTL I 6 STS-12 or STS-3 mode selection. Set HIGH to select the STS-12 operation. Set LOW for STS-3 operation REFCK LVTTL I 7 Local 19.44 MHz reference clock input for the CDR. REFCK is used for the PLL phase adjustment during power up. It also serves as a stable clock source in the absence of serial input data. LCKTOREFN LVTTL I 8 Lock to REFCK input. When set LOW, this pin causes the out- put clock, RXCLKOP/N to be held within +/- 500ppm of the input reference clock REFCL and forces the RXDOP/N to a low state. VSS PWR PWR 9 Ground pin VDD PWR PWR 10 3.3V power supply RXCLKON LVDS/ LVPECL O 11 High-speed clock output, negative. This clock is recovered from the receive data input (RXDIP/N) and supports either LVDS or LVPECL termination RXCLKOP LVDS/ LVPECL O 12 High-speed clock output, positive This clock is recovered from the receive data input (RXDIP/N) and supports either LVDS or LVPECL. termination RXDON LVDS/ LVPECL O 13 High-speed output, negative This is the retimed version of the recovered data stream from RXDIP/N and can be in either LVDS or LVPECL termination RXDOP LVDS/ LVPECL O 14 High-speed output, positive. This is the retimed version of the recovered data stream from RXDIP/N and can be in either LVDS or LVPECL termination |
Similar Part No. - XRT91L33IG |
|
Similar Description - XRT91L33IG |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |