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XRT91L33IG Datasheet(PDF) 5 Page - Exar Corporation |
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XRT91L33IG Datasheet(HTML) 5 Page - Exar Corporation |
5 / 16 page XRT91L33 5 REV. V1.0.0 STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT SIGD LVPECL I 15 Signal detect. SIGD should be connected to the SIGD output on the optical module. SIGD is active HIGH. When SIGD is set HIGH, it means there is sufficient optical power. When SIGD is LOW, this indicates an LOS condition, the RXCLKOP/N output signal will be held to within +/- 500 ppm of the REFCK input. Additionally, the RXDOP/N will be held in the LOW state. TEST LVTTL I 16 Used for production testing. Set to VSS for normal operation. CAP- Analog I 17 Negative side of the external loop filter. The loop filter capacitor should be connected to these pins. The capacitor value should be 1.0 μF +/- 10 % CAP+ Analog I 18 Positive side of the external loop filter. The loop filter capacitor should be connected to these pins. The capacitor value should be 1.0 μF +/- 10 %. VSSA PWR PWR 19 Ground pin VDDA PWR PWR 20 3.3V power supply NAME LEVEL TYPE PIN DESCRIPTION |
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