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XR17V258IV Datasheet(PDF) 9 Page - Exar Corporation |
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XR17V258IV Datasheet(HTML) 9 Page - Exar Corporation |
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9 / 70 page  XR17V258 9 REV. 1.0.1 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT 1.0 XR17V258 INTERNAL REGISTERS The XR17V258 UART has three different sets of registers as shown in Figure 3. The PCI Local Bus Configuration Space Registers are for plug-and-play auto-configuration when connecting the device to the PCI bus. This auto-configuration feature makes installation very easy into a PCI system and it is part of the PCI local bus specification. The second register set is the Device Configuration Registers that are also accessible directly from the PCI bus for programming general operating conditions of the device and monitoring the status of various functions common to all eight channels. These functions include all 8 channel UARTs’ interrupt control and status, 16-bit general purpose timer control and status, multipurpose inputs/ outputs control and status, sleep mode, soft-reset, and device identification and revision. And lastly, each UART channel has its own set of internal UART Configuration Registers for its own operation control and status reporting. All 8 sets of channel registers are embedded inside the device configuration registers space, which provides faster access. The second and third set of registers are mapped into 4K of the PCI bus memory address space. The following paragraphs describe all 3 sets of registers in detail. 1.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS The PCI local bus configuration space registers are responsible for setting up the device’s operating environment in the PCI local bus. The pre-defined operating parameters of the device is read by the PCI bus plug-and-play auto-configuration manager in the operating system. After the PCI bus has collected all data from every device/card on the bus, it defines and downloads the memory mapping information to each device/ card about their individual operation memory address location and conditions. The operating memory mapped address location is downloaded into the Base Address Register (BAR) register, located at an address offset of 0x10 in the configuration space. Custom modification of certain registers is possible by using an external 93C46 EEPROM. The EEPROM contains the device vendor and sub-vendor data, along with 6 other words of information (see “Section 1.4, EEPROM Interface” on page 14) required by the auto-configuration setup. FIGURE 3. THE XR17V258 REGISTER SETS C hannel 0 IN T , M PIO , TIM ER ,REG D evic e C onfig ur ation and U AR T [7:0] C onfig ur ation R eg is ter s ar e mapped on to the Bas e Addr es s R eg is ter ( BAR ) in a 4K- byte of memor y addr es s s pac e PC I Loc al Bus Inter fac e C hannel 0 C hannel 1 C hannel 2 C hannel 3 C hannel 4 C hannel 5 C hannel 6 C hannel 7 D evic e C onfig ur ation R eg is ter s 8 c hannel Inter r upts , M ultipur pos e I/O s , 16- bit T imer /C ounter , Sleep, R es et, D VID , D R EV U AR T [7:0] C onfig ur ation Reg is ter s 16550 C ompatible and EXAR Enhanc ed R eg is ter s PC I Loc al Bus C onfig ur ation Spac e R eg ister s for Plug - and- Play Auto C onfig ur ation PCI REG S-1 Vendor and Sub- vendor ID and Pr oduc t M odel N umber in Exter nal EEPR O M 0x 00 00 0x 02 00 0x 04 00 0x 06 00 0x 08 00 0x 0A 0 0 0x0C 00 0x0E00 0x 00 80 0x0F F F |
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