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CS8427-CSZR Datasheet(PDF) 3 Page - Cirrus Logic |
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CS8427-CSZR Datasheet(HTML) 3 Page - Cirrus Logic |
3 / 60 page CS8427 DS477F4 3 11.14 Receiver Error (10h) (Read Only)................................................................................. 35 11.15 Receiver Error Mask (11h) ........................................................................................... 36 11.16 Channel Status Data Buffer Control (12h) .................................................................... 36 11.17 User Data Buffer Control (13h) ..................................................................................... 37 11.18 Q-Channel Subcode Bytes 0 to 9 (14h - 1Dh) (Read Only) ......................................... 37 11.19 OMCK/RMCK Ratio (1Eh) (Read Only)........................................................................ 38 11.20 C-bit or U-bit Data Buffer (20h - 37h) ........................................................................... 38 11.21 CS8427 I.D. and Version Register (7Fh) (Read Only) ................................................. 38 12. PIN DESCRIPTION - SOFTWARE MODE ........................................................................... 39 13. HARDWARE MODE DESCRIPTION ................................................................................... 42 13.1 Serial Audio Port Formats ............................................................................................. 42 14. PIN DESCRIPTION - HARDWARE MODE .......................................................................... 44 15. APPLICATIONS ................................................................................................................... 46 15.1 Reset, Power Down and Start-up .................................................................................. 46 15.2 ID Code and Revision Code .......................................................................................... 46 15.3 Power Supply, Grounding, and PCB layout ................................................................... 46 15.4 Synchronization of Multiple CS8427s ............................................................................ 46 16. PACKAGE DIMENSIONS .................................................................................................... 47 17. ORDERING INFORMATION ............................................................................................... 49 18. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER AND RECEIVER COMPO- NENTS .................................................................................................................................. 50 18.1 AES3 Transmitter External Components ....................................................................... 50 18.2 Isolating Transformer Requirements ............................................................................. 50 18.3 AES3 Receiver External Components ........................................................................... 51 18.4 Isolating Transformer Requirements ............................................................................. 51 19. APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT ........... 52 19.1 AES3 Channel Status(C) Bit Management .................................................................... 52 19.1.1 Manually accessing the E buffer ....................................................................... 52 19.1.2 Reserving the first 5 bytes in the E buffer ......................................................... 53 19.1.3 Serial Copy Management System (SCMS) ....................................................... 53 19.1.4 Channel Status Data E Buffer Access .............................................................. 53 19.2 AES3 User (U) Bit Management .................................................................................... 54 19.2.1 Mode 1: Transmit All Zeros ............................................................................... 54 19.2.2 Mode 2: Block Mode ......................................................................................... 54 20. APPENDIX C: PLL FILTER .................................................................................................. 55 20.1 General .......................................................................................................................... 55 20.2 External Filter Components ........................................................................................... 56 20.2.1 General ............................................................................................................. 56 20.2.2 Capacitor Selection ........................................................................................... 56 20.2.3 Circuit Board Layout ......................................................................................... 56 20.3 Component Value Selection .......................................................................................... 57 20.3.1 Identifying the Part Revision ............................................................................. 57 20.3.2 Locking to the RXP/RXN Receiver Inputs ......................................................... 57 20.3.3 Locking to the ILRCK Input ............................................................................... 58 20.3.4 Jitter Tolerance ................................................................................................. 58 20.3.5 Jitter Attenuation ............................................................................................... 59 21. REVISION HISTORY ............................................................................................................ 60 |
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