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MPC89L53AE Datasheet(PDF) 10 Page - Megawin Technology Co., Ltd |
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MPC89L53AE Datasheet(HTML) 10 Page - Megawin Technology Co., Ltd |
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10 / 38 page  Nonvolatile Registers: There are two Nonvolatile Registers named OR0 and OR1 individually. They are designed to configure the MPC89x53A options. Generally these two nonvolatile registers will be written via a popular NVM writer, i.e., Hi-Lo System All-11, Leaper-48 and Megawin-Provided MCU writer. Furthermore, the user can change the NVM register OR1 by the ISP program, but OR0 can only be written via an off-line popular NVM writer. NVM register: OR0 (Option Register 0): Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 - - ISPAS1 ISPAS0 - MOVCL SB LOCK {ISPAS1, ISPAS0}: Used to identify the start address for ISP program {0, 0}:= The ISP space is from 0x2C00 to 0x3BFF (4K size). {0, 1}:= The ISP space is from 0x3400 to 0x3BFF (2K size). {1, 0}:= The ISP space is from 0x3800 to 0x3BFF (1K size) {1, 1}:= No ISP space. These two bits decide where the ISP program locates. MOVCL: Used to determine if MOVC instruction will be disabled. 0:= MOVC is conditionally disabled. 1:= MOVC is always available. SB: Used to determine if the program code will be scrambled while it is dumped. 0:= Code dump from Writer is scrambled. 1:= Code dump from Writer is transparent. LOCK: Used to determine if the program code will be locked against the popular writer. 0:= lock code. 1:= does not lock code If the code is locked, all the data dumped from a popular will always show FFh. Please check file “initial Configuration.pdf” to get the default value of the OR0. 10 MPC89x53A Data Sheet MEGAWIN |
Similar Part No. - MPC89L53AE |
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Similar Description - MPC89L53AE |
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