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M12S128168A Datasheet(PDF) 6 Page - Elite Semiconductor Memory Technology Inc. |
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M12S128168A Datasheet(HTML) 6 Page - Elite Semiconductor Memory Technology Inc. |
6 / 45 page ESMT M12S128168A Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2008 Revision: 1.1 6/45 AC OPERATING TEST CONDITIONS (VDD = 2.5V ± 0.2V,TA = 0 to 70 C ° ) Parameter Value Unit Input levels (Vih/Vil) 0.9xVDDQ/0.2 V Input timing measurement reference level 0.5xVDDQ V Input rise and fall-time tr/tf = 1/1 ns Output timing measurement reference level 0.5xVDDQ V Output load condition See Fig. 2 (Fig. 1) DC Output Load Circuit (Fig. 2) AC Output Load Circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Version Parameter Symbol -6 -7 -8 Unit Note Row active to row active delay tRRD(min) 12 14 20 ns 1 RAS to CAS delay tRCD(min) 18 20 30 ns 1 Row precharge time tRP(min) 18 20 30 ns 1 tRAS(min) 40 42 60 ns 1 Row active time tRAS(max) 100 us @ Operating tRC(min) 58 63 90 ns 1 Row cycle time @ Auto refresh tRFC(min) 60 70 100 ns 1,5 Last data in to col. address delay tCDL(min) 1 tCK 2 Last data in to row precharge tRDL(min) 2 tCK 2 Last data in to burst stop tBDL(min) 1 tCK 2 Refresh period (4,096 rows) tREF(max) 64 ms 6 |
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