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M13S64322A Datasheet(PDF) 10 Page - Elite Semiconductor Memory Technology Inc. |
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M13S64322A Datasheet(HTML) 10 Page - Elite Semiconductor Memory Technology Inc. |
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10 / 49 page  ESMT Preliminary M13S64322A Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 10/49 Basic Functionality Power-Up and Initialization Sequence The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.) - Apply VDD before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VTT & VREF). 2. Start clock and maintain stable condition for a minimun of 200us. 3. The minimun of 200us after stable power and clock (CLK, CLK ), apply NOP & take CKE high. 4. Issue precharge commands for all banks of the device. *1 5. Issue EMRS to enable DLL. *1 6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is required to lock the DLL. *2 7. Issue precharge commands for all banks of the device. 8. Issue 2 or more auto-refresh commands. 9. Issue a mode register set command with low to A8 to initialize device operation. *1 Every “DLL enable” command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it, the additional 200 cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6 & 7 is regardless of the order. CL K CLK Co m m a n d 2 13 45 6 7 8 910 11 12 13 14 15 16 17 18 19 0 t RP pr ech a r g e Al l B a n k s EM R S MR S Dl l R e s e t t RP pr ec h a r g e Al l Ban k s 1 s t A u to Re f r e s h t RC 2nd A u t o Re f r e s h t RC Mode Regi ster Set An y Co m m a n d m i n . 20 0 Cy c l e P o we r up & I n i t i a l i z at i on S e que nc e |
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