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M13S128168A-4BG Datasheet(PDF) 7 Page - Elite Semiconductor Memory Technology Inc.

Part # M13S128168A-4BG
Description  2M x 16 Bit x 4 Banks Double Data Rate SDRAM
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Manufacturer  ESMT [Elite Semiconductor Memory Technology Inc.]
Direct Link  http://www.esmt.com.tw/index.asp
Logo ESMT - Elite Semiconductor Memory Technology Inc.

M13S128168A-4BG Datasheet(HTML) 7 Page - Elite Semiconductor Memory Technology Inc.

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ESMT
M13S128168A
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008
Revision : 2.2
7/49
AC Timing Parameter & Specifications-continued
-4
-5
-6
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Half Clock Period
tHP
tCLmin or
tCHmin
-
tCLmin or
tCHmin
-
tCLmin or
tCHmin
-
ns
DQ-DQS output hold time
tQH
tHP-tQHS
-
tHP-tQHS
-
tHP-tQHS
-
ns
Data hold skew factor
tQHS
-
0.5
-
0.45
-
0.5
ns
ACTIVE to PRECHARGE command
tRAS
40
70K
40
70K
42
70K
ns
Row Cycle Time
tRC
52
-
60
-
60
-
ns
AUTO REFRESH Row Cycle Time
tRFC
60
-
70
-
72
-
ns
ACTIVE to READ,WRITE delay
tRCD
15
-
15
-
18
-
ns
PRECHARGE command period
tRP
15
-
15
-
18
-
ns
ACTIVE to READ with
AUTOPRECHARGE command
tRAP
18
-
18
-
18
-
ns
ACTIVE bank A to ACTIVE bank B
command
tRRD
10
-
10
-
12
-
ns
Write recovery time
tWR
15
-
15
-
15
-
ns
Write data in to READ command delay
tWTR
2
-
2
-
2
-
tCK
Col. Address to Col. Address delay
tCCD
1
-
1
-
1
-
tCK
Average periodic refresh interval
tREFI
-
15.6
-
15.6
-
15.6
us
Write preamble
tWPRE
0.25
-
0.25
-
0.25
-
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Clock to DQS write preamble setup
time
tWPRES
0
-
0
-
0
-
ns
Load Mode Register / Extended Mode
register cycle time
tMRD
2
-
2
-
1
-
tCK
Exit self refresh to READ command
tXSRD
200
-
200
-
200
-
tCK
Exit self refresh to non-READ
command
tXSNR
75
-
75
-
75
-
ns
Autoprecharge write
recovery+Precharge time
tDAL
(tWR/tCK)
+
(tRP/tCK)
-
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
tCK


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