ESMT

M13S5121632A

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2008

Revision : 1.0

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AC Timing Parameter & Specifications-continued

-5

Parameter

Symbol

min

max

Unit

Note

Half Clock Period

-

ns

DQ-DQS output hold time

-

ns

Data hold skew factor

-

0.5

ns

ACTIVE to PRECHARGE command

40

70K

ns

Row Cycle Time

55

-

ns

AUTO REFRESH Row Cycle Time

70

-

ns

ACTIVE to READ,WRITE delay

15

-

ns

PRECHARGE command period

15

-

ns

ACTIVE bank A to ACTIVE bank B

command

10

-

ns

Write recovery time

15

-

ns

Write data in to READ command delay

2

-

Average periodic refresh interval

-

7.8

us

4

Write preamble

0.25

-

3

Write postamble

0.4

0.6

2

DQS read preamble

0.9

1.1

DQS read postamble

0.4

0.6

Clock to DQS write preamble setup

time

0

-

ns

Load Mode Register / Extended Mode

register cycle time

10

-

ns

Exit self refresh to READ command

200

-

Exit self refresh to non-READ

command

75

-

ns

Autoprecharge write

recovery+Precharge time

30

-

ns

Note :

1.

to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving (LZ).

2.

The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but

system performance (bus turnaround) will degrade accordingly.

3.

The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CLK edge.

A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. When no writes were

previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous write was in progress,

4.

A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.

5.

For command/address and CLK & CLK slew rate > 1.0V/ns.