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M14D5121632A-2.5BG Datasheet(PDF) 6 Page - Elite Semiconductor Memory Technology Inc. |
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M14D5121632A-2.5BG Datasheet(HTML) 6 Page - Elite Semiconductor Memory Technology Inc. |
6 / 59 page ESMT M14D5121632A Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2009 Revision : 1.1 6/59 DC Specifications (IDD values are for the operation range of Voltage and Temperature) Version Parameter Symbol Test Condition -2.5 -3 Unit Operating Current (Active - Precharge) IDD0 One bank; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS (IDD)min; CKE is High, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING 70 65 mA Operating Current (Active - Read - Precharge) IDD1 One bank; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS (IDD)min, tRCD = tRCD (IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W 85 80 mA Precharge Power-Down Standby Current IDD2P All banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING 10 10 mA Precharge Quiet Standby Current IDD2Q All banks idle; tCK = tCK (IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING 15 15 mA Idle Standby Current IDD2N All banks idle; tCK = tCK (IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING 20 20 mA Fast PDN Exit MRS(12) = 0 15 15 Active Power-down Standby Current IDD3P All banks open; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus input are FLOATING Slow PDN Exit MRS(12) = 1 12 12 mA Active Standby Current IDD3N All banks open; tCK = tCK (IDD), tRAS = tRAS (IDD)max, tRP = tRP (IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING 40 35 mA Operation Current (Read) IDD4R All banks open, continuous burst Reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS (IDD)max, tRP = tRP (IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is the same as IDD4W; 170 145 mA Operation Current (Write) IDD4W All banks open, continuous burst Writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS (IDD)max, tRP = tRP (IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING 160 140 mA |
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