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M24L216128DA-55BEG Datasheet(PDF) 5 Page - Elite Semiconductor Memory Technology Inc. |
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M24L216128DA-55BEG Datasheet(HTML) 5 Page - Elite Semiconductor Memory Technology Inc. |
5 / 14 page ESMT M24L216128DA Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008 Revision : 1.2 5/14 AC Test Loads and Waveforms Parameters 3.0V VCC Unit R1 22000 Ω R2 22000 Ω RTH 11000 Ω VTH 1.50 V Switching Characteristics Over the Operating Range[10] -55 [14] -70 Parameter Description Min. Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 55[14] 70 ns tAA Address to Data Valid 55 70 ns tOHA Data Hold from Address Change 5 10 ns tACE 1 CE LOW and CE2 HIGH to Data Valid 55 70 ns tDOE OE LOW to Data Valid 25 35 ns tLZOE OE LOW to LOW Z[11, 12] 5 5 ns tHZOE OE HIGH to High Z[11, 12] 25 25 ns tLZCE 1 CE LOW and CE2 HIGH to Low Z[11, 12] 2 5 ns tHZCE 1 CE HIGH and CE2 LOW to High Z[11, 12] 25 25 ns tDBE BLE / BHE LOW to Data Valid 55 70 ns tLZBE BLE / BHE LOW to Low Z[11, 12] 5 5 ns tHZBE BLE / BHE HIGH to High Z[11, 12] 10 25 ns tSK[14] Address Skew 0 10 ns Write Cycle[12] tWC Write Cycle Time 55 70 ns tSCE 1 CE LOW and CE2 HIGH to Write End 45 55 ns tAW Address Set-Up to Write End 45 55 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns Notes: 10. Test conditions assume signal transition time of 1 V/ns or higher, timing reference levels of VCC(typ)/2, input pulse levels of 0V to VCC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance. 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 12. High-Z and Low-Z parameters are characterized and are not 100% tested. 13. The internal write time of the memory is defined by the overlap of WE , 1 CE = VIL, CE2 = VIH, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates write. 14. To achieve 55-ns performance, the read access should be Chip-enable controlled. In this case tACE is the critical parameter and tSK is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle. |
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