ESMT

M24L48512SA

Elite Semiconductor Memory Technology Inc.

Publication Date: Jul. 2008

Revision: 1.1

8/12

Avoid Timing

ESMT Pseudo SRAM has a timing which is not supported at read operation, If your system has multiple invalid address signal

shorter than tRC during over 15μs at read operation shown as in Abnormal Timing, it requires a normal read timing at leat during

Abnormal Timing

Avoidable Timing 1

Avoidable Timing 2

CE

≧

15μ s

WE

Address

＜

CE

≧

15μ s

WE

Address

t

CE

≧

15μ s

WE

Address

＜

t