ESMT

M24L416256SA

Elite Semiconductor Memory Technology Inc.

Publication Date: Jul. 2008

Revision: 1.4

9/14

Avoid Timing

ESMT Pseudo SRAM has a timing which is not supported at read operation, If your system has multiple invalid address signal

Abnormal Timing

Avoidable Timing 1

Avoidable Timing 2

CE

≧

15μ s

WE

Address

＜

CE

≧

15μ s

WE

Address

t

CE

≧

15μ s

WE

Address

＜

t