ESMT

M24L416256SA

Elite Semiconductor Memory Technology Inc.

Publication Date: Jul. 2008

Revision: 1.4

5/14

AC Test Loads and Waveforms

Parameters

Unit

R1

22000

Ω

R2

22000

Ω

11000

Ω

1.50

V

Switching Characteristics (Over the Operating Range)[10]

–55

–60

–70

Prameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Read Cycle

Read Cycle Time

55

60

70

ns

Address to Data Valid

55

60

70

ns

Data Hold from Address Change

5

8

10

ns

CE LOW to Data Valid

55

60

70

ns

OE LOW to Data Valid

25

25

35

ns

OE LOW to Low Z[11, 13]

5

5

5

ns

OE HIGH to High Z[11, 13]

25

25

25

ns

CE LOW to Low Z[11, 13]

2

2

5

ns

CE HIGH to High Z[11, 13]

25

25

25

ns

BLE / BHE LOW to Data Valid

55

60

70

ns

BLE

/ BHE LOW to Low Z[11, 13]

5

5

5

ns

BLE

/ BHE HIGH to High-Z[11, 13]

10

10

25

ns

[14]

Address Skew

0

5

10

ns

Write Cycle[12]

Write Cycle Time

55

60

70

ns

CE LOW to Write End

45

45

60

ns

Address Set-up to Write End

45

45

55

ns

Address Hold from Write End

0

0

0

ns

Address Set-up to Write Start

0

0

0

ns

WE

Pulse Width

40

40

45

ns

Notes:

10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference

Loads and Waveforms” section.

must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up

and hold timing should be referenced to the edge of the signal that terminates the write.

13. High-Z and Low-Z parameters are characterized and are not 100% tested.

satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable

within 10 ns after the start of the read cycle.