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M24L416256SA-55TEG Datasheet(PDF) 5 Page - Elite Semiconductor Memory Technology Inc. |
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M24L416256SA-55TEG Datasheet(HTML) 5 Page - Elite Semiconductor Memory Technology Inc. |
5 / 14 page ESMT M24L416256SA Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.4 5/14 AC Test Loads and Waveforms Parameters 3.0V VCC Unit R1 22000 Ω R2 22000 Ω RTH 11000 Ω VTH 1.50 V Switching Characteristics (Over the Operating Range)[10] –55 –60 –70 Prameter Description Min. Max. Min. Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 55 60 70 ns tAA Address to Data Valid 55 60 70 ns tOHA Data Hold from Address Change 5 8 10 ns tACE CE LOW to Data Valid 55 60 70 ns tDOE OE LOW to Data Valid 25 25 35 ns tLZOE OE LOW to Low Z[11, 13] 5 5 5 ns tHZOE OE HIGH to High Z[11, 13] 25 25 25 ns tLZCE CE LOW to Low Z[11, 13] 2 2 5 ns tHZCE CE HIGH to High Z[11, 13] 25 25 25 ns tDBE BLE / BHE LOW to Data Valid 55 60 70 ns tLZBE BLE / BHE LOW to Low Z[11, 13] 5 5 5 ns tHZBE BLE / BHE HIGH to High-Z[11, 13] 10 10 25 ns tSK [14] Address Skew 0 5 10 ns Write Cycle[12] tWC Write Cycle Time 55 60 70 ns tSCE CE LOW to Write End 45 45 60 ns tAW Address Set-up to Write End 45 45 55 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-up to Write Start 0 0 0 ns tPWE WE Pulse Width 40 40 45 ns Notes: 10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels of 0V to V CC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 12. The internal Write time of the memory is defined by the overlap of WE , CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 13. High-Z and Low-Z parameters are characterized and are not 100% tested. 14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle. |
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