ESMT

M24L816512SA

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2009

Revision : 1.5

5/14

AC Test Loads and Waveforms

Parameters

Unit

R1

22000

Ω

R2

22000

Ω

11000

Ω

1.50

V

Switching Characteristics Over the Operating Range[10, 11, 12, 13, 14]

-55

-70

Parameter

Description

Min.

Max.

Min.

Max.

Unit

Read Cycle

Read Cycle Time

55[14]

70

ns

Address to Data Valid

55

70

ns

Data Hold from Address Change

5

5

ns

CE LOW to Data Valid

55

70

ns

OE LOW to Data Valid

25

35

ns

OE LOW to LOW Z[11, 12]

5

5

ns

OE HIGH to High Z[11, 12]

25

25

ns

CE LOW to Low Z[11, 12]

5

5

ns

CE HIGH to High Z[11, 12]

25

25

ns

BLE

/ BHE LOW to Data Valid

55

70

ns

BLE

/ BHE LOW to Low Z[11, 12]

5

5

ns

BLE

/ BHE HIGH to High Z[11, 12]

10

25

ns

Address Skew

0

10

ns

Notes:

12. High-Z and Low-Z parameters are characterized and are not 100% tested.

must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up

and hold timing should be referenced to the edge of the signal that terminates write.

is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be

stable within 10 ns after the start of the read cycle.