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M24L416256SA-70BIG Datasheet(PDF) 1 Page - Elite Semiconductor Memory Technology Inc. |
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M24L416256SA-70BIG Datasheet(HTML) 1 Page - Elite Semiconductor Memory Technology Inc. |
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1 / 14 page  ESMT M24L416256SA Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.4 1/14 PSRAM 4-Mbit (256K x 16) Pseudo Static RAM Features • Wide voltage range: 2.7V–3.6V • Access time: 55 ns, 60 ns and 70 ns • Ultra-low active power — Typical active current: 1 mA @ f = 1 MHz — Typical active current: 8 mA @ f = fmax (70-ns speed) • Ultra low standby power • Automatic power-down when deselected • CMOS for optimum speed/power Functional Description The M24L416256SA is a high-performance CMOS Pseudo static RAM organized as 256K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for portable applications such as cellular telephones. The device can be put into standby mode when deselected ( CE HIGH or both BHE and BLE are HIGH). The input/output pins (I/O0through I/O15) are placed in a high-impedance state when : deselected ( CE HIGH), outputs are disabled ( OE HIGH), both Byte High Enable and Byte Low Enable are disabled ( BHE , BLE HIGH), or during a write operation ( CE LOW and WE LOW). Writing to the device is accomplished by taking Chip Enable( CE LOW) and Write Enable ( WE ) input LOW. If Byte Low Enable ( BLE ) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins(A0 through A17). If Byte High Enable ( BHE ) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable ( CE LOW) and Output Enable ( OE ) LOW while forcing the Write Enable ( WE ) HIGH. If Byte Low Enable ( BLE ) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable( BHE ) is LOW, then data from memory will appear on I/O8 toI/O15. Refer to the truth table for a complete description of read and write modes. Logic Block Diagram |
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