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M52S32162A-10BIG Datasheet(PDF) 3 Page - Elite Semiconductor Memory Technology Inc. |
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M52S32162A-10BIG Datasheet(HTML) 3 Page - Elite Semiconductor Memory Technology Inc. |
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3 / 30 page  ESMT M52S32162A Operation Temperature Condition -40°C ~85°C Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 3/30 FUNCTIONAL BLOCK DIAGRAM Bank Select Data Input Register Column Decoder Latency & Burst Length Programming Register 1M x 16 1M x 16 Timing Register CLK CKE CS RAS CAS WE L(U)DQM LDQM LWCBR DQi LDQM LWE LRAS LCBR LWE LCAS CLK ADD LCKE PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System Clock Active on the positive going edge to sample all inputs. CS Chip Select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and L(U)DQM. CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A0 ~ A11 Address Row / column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, column address : CA0 ~ CA7 BA Bank Select Address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column Address Strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write Enable Enables write operation and row precharge. Latches data in starting from CAS , WE active. L(U)DQM Data Input / Output Mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. |
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