M52S128324A-10TG datasheet(6/47 Pages) ESMT

Part #	M52S128324A-10TG

Description	1M x 32 Bit x 4 Banks Synchronous DRAM

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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6 / 47 page

ESMT

M52S128324A

Elite Semiconductor Memory Technology Inc.

Publication Date: Mar. 2009

Revision: 1.4

6/47

AC OPERATING TEST CONDITIONS

(VDD = 2.5V ± 0.2V ，TA = 0 to 70 C

°)

Parameter

Value

Unit

Input levels (Vih/Vil)

0.9XVDDQ / 0.2

V

Input timing measurement reference level

0.5xVDDQ

V

Input rise and fall-time

tr/tf = 1/1

ns

Output timing measurement reference level

0.5xVDDQ

V

Output load condition

See Fig. 2

(Fig. 1) DC Output Load Circuit

(Fig. 2) AC Output Load Circuit

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Version

Parameter

Symbol

-7

-10

Unit

Note

Row active to row active delay

tRRD(min)

14

20

ns

1

RAS to CAS delay

tRCD(min)

18

30

ns

1

Row precharge time

tRP(min)

20

30

ns

1

tRAS(min)

42

50

ns

1

Row active time

tRAS(max)

100

us

@ Operating

tRC(min)

70

80

Row cycle time

@ Auto Refresh

tRFC(min)

70

80

ns

1

Last data in to col. address delay

tCDL(min)

1

CLK

2

Last data in to row precharge

tRDL(min)

2

CLK

2

Last data in to burst stop

tBDL(min)

1

CLK

2

Output

VOH (DC) =2.4V , IOH = -2 mA

VOL (DC) =0.4V , IOL = 2 mA

Output

30pF

Z0 =50

30pF

50

Vtt = 0.5xVDDQ

VDDQ

500

Ω

500

Ω

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M52S128324A-10TG Datasheet(PDF) 6 Page - Elite Semiconductor Memory Technology Inc.

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