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M53D128168A-7.5BAG Datasheet(PDF) 1 Page - Elite Semiconductor Memory Technology Inc. |
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M53D128168A-7.5BAG Datasheet(HTML) 1 Page - Elite Semiconductor Memory Technology Inc. |
1 / 47 page ESMT Preliminary M53D128168A Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 1/47 DM DQ Mode Register & Extended Mode Register Column Address Buffer & Refresh Counter Row Address Buffer & Refresh Counter Sense Amplifier Column Decoder Data Control Circuit Address Clock Generator CLK CLK CKE CS RAS CAS WE DQS Mobile DDR SDRAM 2M x 16 Bit x 4 Banks Mobile DDR SDRAM Features JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) No DLL; CLK to DQS is not synchronized. Differential clock inputs (CLK and CLK ) Quad bank operation CAS Latency : 2, 3 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8 Special function support - PASR (Partial Array Self Refresh) - Internal TCSR (Temperature Compensated Self Refresh) - DS (Driver Strength) All inputs except data & DM are sampled at the rising edge of the system clock(CLK) Data I/O transitions on both edges of data strobe (DQS) DQS is edge-aligned with data for READ; center-aligned with data for WRITE Data mask (DM) for write masking only VDD/VDDQ = 1.7V ~ 1.9V Auto & Self refresh 15.6us refresh interval (64ms refresh period, 4K cycle) 1.8V LVCMOS-compatible inputs 60 ball BGA package Ordering information : Part NO. MAX FREQ VDD PACKAGE COMMENTS M53D128168A -7.5BG 133MHz Pb-free M53D128168A -10BG 100MHz 8x10 mm BGA Pb-free M53D128168A -7.5BAG 133MHz Pb-free M53D128168A -10BAG 100MHz 1.8V 8x13 mm BGA Pb-free Functional Block Diagram Bank A Bank D Bank B Bank C |
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