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STM32F103C4H7TR Datasheet(PDF) 11 Page - STMicroelectronics |
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STM32F103C4H7TR Datasheet(HTML) 11 Page - STMicroelectronics |
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11 / 80 page  STM32F103x4, STM32F103x6 Description Doc ID 15060 Rev 3 11/80 Figure 2. Clock tree 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz. 2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either 48 MHz or 72 MHz. 3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz. HSE OSC 4-16 MHz OSC_IN OSC_OUT OSC32_IN OSC32_OUT LSE OSC 32.768 kHz HSI RC 8 MHz LSI RC 40 kHz to Independent Watchdog (IWDG) PLL x2, x3, x4 PLLMUL Legend: MCO Clock Output Main PLLXTPRE /2 ..., x16 AHB Prescaler /1, 2..512 /2 PLLCLK HSI HSE APB1 Prescaler /1, 2, 4, 8, 16 ADC Prescaler /2, 4, 6, 8 ADCCLK PCLK1 HCLK PLLCLK to AHB bus, core, memory and DMA USBCLK to USB interface to TIM2, TIM3 USB Prescaler /1, 1.5 to ADC LSE LSI HSI /128 /2 HSI HSE peripherals to APB1 Peripheral Clock Enable (13 bits) Enable (3 bits) Peripheral Clock APB2 Prescaler /1, 2, 4, 8, 16 PCLK2 to TIM1 peripherals to APB2 Peripheral Clock Enable (11 bits) Enable (1 bit) Peripheral Clock 48 MHz 72 MHz max 72 MHz 72 MHz max 36 MHz max to RTC PLLSRC SW MCO CSS to Cortex System timer /8 Clock Enable (3 bits) SYSCLK max RTCCLK RTCSEL[1:0] TIM1CLK TIMXCLK IWDGCLK SYSCLK FCLK Cortex free running clock TIM2, TIM3 If (APB1 prescaler =1) x1 else x2 TIM1 timer If (APB2 prescaler =1) x1 else x2 HSE = high-speed external clock signal HSI = high-speed internal clock signal LSI = low-speed internal clock signal LSE = low-speed external clock signal ai15176 |
Similar Part No. - STM32F103C4H7TR |
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Similar Description - STM32F103C4H7TR |
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