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MB81EDS516545 Datasheet(PDF) 6 Page - Fujitsu Component Limited. |
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MB81EDS516545 Datasheet(HTML) 6 Page - Fujitsu Component Limited. |
6 / 60 page MB81EDS516545 6 DS05-11463-1E 10. Write Data Strobe (WDQS0 to WDQS3) WDQS is input signal transmitted by the memory controller during write operation. WDQS is center aligned with input data. WDQS0, WDQS1, WDQS2 and WDQS3 correspond to DQ[15:0], DQ[31:16], DQ[47:32] and DQ[63:48] respectively. Refer to the “DQ/RDQS/WDQS/DM Correspondence Table”. • DQ/RDQS/WDQS/DM Correspondence Table 11. Select Area Enable (SA) SA is used to support optional commands of MACT, MPRE and BREF. Refer to the “ ■COMMAND TRUTH TABLE”. SA can be tied to VSS if optional commands are not required. DQ RDQS WDQS DM DQ[7:0] RDQS0 WDQS0 DM0 DQ[15:8] DM1 DQ[23:16] RDQS1 WDQS1 DM2 DQ[31:24] DM3 DQ[39:32] RDQS2 WDQS2 DM4 DQ[47:40] DM5 DQ[55:48] RDQS3 WDQS3 DM6 DQ[63:56] DM7 |
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