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24LC64F Datasheet(PDF) 3 Page - Microchip Technology |
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24LC64F Datasheet(HTML) 3 Page - Microchip Technology |
3 / 30 page © 2009 Microchip Technology Inc. DS22154A-page 3 24AA64F/24LC64F TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Electrical Characteristics: Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to 125°C Param. No. Sym. Characteristic Min. Max. Units Conditions 1FCLK Clock frequency — — 100 400 kHz 1.7V ≤ VCC < 2.5V 2.5V ≤ VCC ≤ 5.5V 2THIGH Clock high time 4000 600 — — ns 1.7V ≤ VCC < 2.5V 2.5V ≤ VCC ≤ 5.5V 3TLOW Clock low time 4700 1300 — — ns 1.7V ≤ VCC < 2.5V 2.5V ≤ VCC ≤ 5.5V 4TR SDA and SCL rise time (Note 1) — — 1000 300 ns 1.7V ≤ VCC < 2.5V 2.5V ≤ VCC ≤ 5.5V 5TF SDA and SCL fall time (Note 1) — 300 ns — 6THD:STA Start condition hold time 4000 600 — — ns 1.7V ≤ VCC < 2.5V 2.5V ≤ VCC ≤ 5.5V 7TSU:STA Start condition setup time 4700 600 — — ns 1.7V ≤ VCC < 2.5V 2.5V ≤ VCC ≤ 5.5V 8THD:DAT Data input hold time 0 — ns (Note 2) 9TSU:DAT Data input setup time 250 100 — — ns 1.7V ≤ VCC < 2.5V 2.5V ≤ VCC ≤ 5.5V 10 TSU:STO Stop condition setup time 4000 600 — — ns 1.7 V ≤ VCC < 2.5V 2.5 V ≤ VCC ≤ 5.5V 11 TSU:WP WP setup time 4000 600 — — ns 1.7V ≤ VCC < 2.5V 2.5V ≤ VCC ≤ 5.5V 12 THD:WP WP hold time 4700 1300 — — ns 1.7V ≤ VCC < 2.5V 2.5V ≤ VCC ≤ 5.5V 13 TAA Output valid from clock (Note 2) — — 3500 900 ns 1.7V ≤ VCC < 2.5V 2.5V ≤ VCC ≤ 5.5V 14 TBUF Bus free time: Time the bus must be free before a new transmission can start 4700 1300 — — ns 1.7V ≤ VCC < 2.5V 2.5V ≤ VCC ≤ 5.5V 15 TOF Output fall time from VIH minimum to VIL maximum CB ≤ 100 pF 10 + 0.1CB 250 ns (Note 1) 16 TSP Input filter spike suppression (SDA and SCL pins) —50 ns (Notes 1 and 3) 17 TWC Write cycle time (byte or page) —5 ms — 18 — Endurance 1,000,000 — cycles 25°C (Note 4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site at www.microchip.com. |
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