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M68000 Datasheet(PDF) 7 Page - Motorola, Inc |
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M68000 Datasheet(HTML) 7 Page - Motorola, Inc |
7 / 26 page 7 M68000 USER’S MANUAL ADDENDUM MOTOROLA After the previous steps are completed, the MC68SEC000 will remain in the low-power mode until it recognizes the appropriate interrupt . External logic will also have to poll IPLB2–IPLB0 to detect the proper interrupt. When the correct interrupt level is received, the following steps will bring the processor out of the low-power mode: 1. Restart the system clock if it was stopped. 2. Wait for the system clock to become stable. 3. Assert the RESTART signal. This will cause the processor’s clock to start on the next falling edge of the system clock. Figure 6 shows the timing for bringing the processor out of the low-power mode. Both the RESTART and RESET signals are subject to the asynchronous setup time as specified in the Electrical Characteristics section of this addendum. WARNING The system clock must be stable before the RESTART signal is asserted to prevent glitches in the clock. An unstable clock can cause unpredictable results in the MC68SEC000. Figure 6. MC68SEC000 Clock Start Timing 4. If the MC68SEC000 was placed in a three-state condition, the BR signal must be negated before the processor can begin executing instructions. CLK CPU_CLK RESTART |
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