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EBE41AE4ACFA Datasheet(PDF) 4 Page - Elpida Memory |
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EBE41AE4ACFA Datasheet(HTML) 4 Page - Elpida Memory |
4 / 27 page EBE41AE4ACFA Data Sheet E1078E40 (Ver. 4.0) 4 Pin Description Pin name Function A0 to A13 Address input Row address A0 to A13 Column address A0 to A9, A11 A10 (AP) Auto precharge BA0, BA1, BA2 Bank select address DQ0 to DQ63 Data input/output CB0 to CB7 Check bit (Data input/output) /RAS Row address strobe command /CAS Column address strobe command /WE Write enable /CS0, /CS1 Chip select CKE0, CKE1 Clock enable CK0 Clock input /CK0 Differential clock input DQS0 to DQS17, /DQS0 to /DQS17 Input and output data strobe SCL Clock input for serial PD SDA Data input/output for serial PD SA0 to SA2 Serial address input VDD Power for internal circuit VDDSPD Power for serial EEPROM VREF Input reference voltage VSS Ground ODT0, ODT1 ODT control /RESET Reset pin (forces register and PLL inputs low) * 1 Par _In*2 Parity bit for the address and control bus /Err _Out*2 Parity error found on the address and control bus NC No connection Notes: 1. Reset pin is connected to both OE of PLL and reset to register. 2. /Err _Out (Pin No. 55) and Par_In (Pin No. 68) are for optional function to check address and command parity. |
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