EDE2516AEBG-6E-E datasheet(9/77 Pages) ELPIDA

Part #	EDE2516AEBG-6E-E

Description	256M bits DDR2 SDRAM

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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EDE2508AEBG, EDE2516AEBG

Data Sheet E1175E20 (Ver. 2.0)

9

×8

×16

Parameter

Symbol

Grade

max.

Unit

Test condition

Auto-refresh current

IDD5

-8E

-6E

90

85

90

85

mA

tCK = tCK (IDD);

Refresh command at every tRFC (IDD)

interval;

CKE is H, /CS is H between valid commands;

Other control and address bus inputs are

SWITCHING;

Data bus inputs are SWITCHING

Self-refresh current

IDD6*

7

4

mA

Self-Refresh Mode;

CK and /CK at 0V; CKE

≤ 0.2V;

Other control and address bus inputs are

FLOATING;

Data bus inputs are FLOATING

Operating current

(Bank interleaving)

IDD7

-8E

-6E

155

165

160

mA

all bank interleaving reads, IOUT = 0mA;

BL = 4, CL = CL(IDD),

AL = tRCD (IDD)

−1

× tCK (IDD);

tCK = tCK (IDD), tRC = tRC (IDD),

tRRD = tRRD(IDD), tRCD = 1

× tCK (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are STABLE during

DESELECTs; Data pattern is same as IDD4W

Notes: 1. IDD specifications are tested after the device is properly initialized.

2. Input slew rate is specified by AC Input Test Condition.

3. IDD parameters are specified with ODT disabled.

4. Data bus consists of DQ, DM, DQS, /DQS, RDQS and /RDQS.

IDD values must be met with all

combinations of EMRS bits 10 and 11.

5. Definitions for IDD

L is defined as VIN

≤ VIL (AC) (max.)

H is defined as VIN

≥ VIH (AC) (min.)

STABLE is defined as inputs stable at an H or L level

FLOATING is defined as inputs at VREF = VDDQ/2

SWITCHING is defined as:

inputs changing between H and L every other clock cycle (once per two clocks) for address and control

signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals

not including masks or strobes.

6. Refer to AC Timing for IDD Test Conditions.

7. When TC

≥ +85°C, IDD6 must be derated by 80%.

IDD6 will increase by this amount, if TC

≥ +85°C and double refresh option is still enabled.

AC Timing for IDD Test Conditions

For purposes of IDD testing, the following parameters are to be utilized.

DDR2-800

DDR2-667

Parameter

5-5-5

Unit

CL (IDD)

5

tCK

tRCD (IDD)

12.5

15

ns

tRC (IDD)

57.5

60

ns

tRRD (IDD)

7.5

ns

tCK (IDD)

2.5

3

ns

tRAS (min.)(IDD)

45

ns

tRAS (max.)(IDD)

70000

ns

tRP (IDD)

12.5

15

ns

tRFC (IDD)

75

ns

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EDE2516AEBG-6E-E Datasheet(PDF) 9 Page - Elpida Memory

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