EDD5116AGTA-4B-E datasheet(7/50 Pages) ELPIDA

Part #	EDD5116AGTA-4B-E

Description	512M bits DDR SDRAM

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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EDD5108AGTA-4, EDD5116AGTA-4

Data Sheet E1195E20 (Ver. 2.0)

7

Pin Capacitance (TA = +25°C, VDD, VDDQ = 2.5V ± 0.125V, VSS, VSSQ = 0V)

Parameter

Symbol

Pins

min.

typ.

max.

Unit

Notes

Input capacitance

CI1

CK, /CK

2.0

—

3.0

pF

1

CI2

All other input pins

2.0

—

3.0

pF

1

Delta input capacitance

Cdi1

CK, /CK

—

0.25

pF

1

Cdi2

All other input-only pins

—

0.5

pF

1

Data input/output capacitance

CI/O

DQ, DM, DQS

4.0

—

5

pF

1, 2

Delta input/output capacitance

Cdio

DQ, DM, DQS

—

0.5

pF

1

Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2,

ΔVOUT = 0.2V.

2. DOUT circuits are disabled.

AC Characteristics (TA = 0

°C to +70°C, VDD, VDDQ = 2.5V ± 0.125V, VSS, VSSQ = 0V)

-4B

-4C

Parameter

Symbol

min.

max.

min.

max.

Unit

Notes

Clock cycle time

tCK

4

8

4

8

ns

10

CK high-level width

tCH

0.45

0.55

0.45

0.55

tCK

CK low-level width

tCL

0.45

0.55

0.45

0.55

tCK

CK half period

tHP

min

(tCH, tCL)

—

min

(tCH, tCL)

—

tCK

DQ output access time from CK, /CK

tAC

–0.7

0.7

–0.7

0.7

ns

2, 11

DQS output access time from CK, /CK

tDQSCK

–0.55

0.55

–0.55

0.55

ns

2, 11

DQS to DQ skew

tDQSQ

—

0.4

—

0.4

ns

3

DQ/DQS output hold time from DQS

tQH

tHP – tQHS —

ns

Data hold skew factor

tQHS

—

0.5

—

0.5

ns

Data-out high-impedance time

from CK, /CK

tHZ

—

0.7

—

0.7

ns

5, 11

Data-out low-impedance time

from CK, /CK

tLZ

–0.7

0.7

–0.7

0.7

ns

6, 11

Read preamble

tRPRE

0.9

1.1

0.9

1.1

tCK

Read postamble

tRPST

0.4

0.6

0.4

0.6

tCK

DQ and DM input setup time

tDS

0.4

—

0.4

—

ns

8

DQ and DM input hold time

tDH

0.4

—

0.4

—

ns

8

DQ and DM input pulse width

tDIPW

1.75

—

1.75

—

ns

7

Write preamble setup time

tWPRES

0

—

0

—

ns

Write preamble

tWPRE

0.3

—

0.3

—

tCK

Write postamble

tWPST

0.4

0.6

0.4

0.6

tCK

9

Write command to first DQS latching transition tDQSS

0.85

1.15

0.85

1.15

tCK

DQS falling edge to CK setup time

tDSS

0.3

—

0.3

—

tCK

DQS falling edge hold time from CK

tDSH

0.3

—

0.3

—

tCK

DQS input high pulse width

tDQSH

0.4

—

0.4

—

tCK

DQS input low pulse width

tDQSL

0.4

—

0.4

—

tCK

Address and control input setup time

tIS

0.6

—

0.6

—

ns

8

Address and control input hold time

tIH

0.6

—

0.6

—

ns

8

Address and control input pulse width

tIPW

2.2

—

2.2

—

ns

7

Mode register set command cycle time

tMRD

3

—

3

—

tCK

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