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EDE1116AEBG-6E-F Datasheet(PDF) 10 Page - Elpida Memory |
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EDE1116AEBG-6E-F Datasheet(HTML) 10 Page - Elpida Memory |
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10 / 78 page  EDE1108AEBG, EDE1116AEBG Preliminary Data Sheet E1228E20 (Ver. 2.0) 10 AC Timing for IDD Test Conditions For purposes of IDD testing, the following parameters are to be utilized. DDR2-800 DDR2-667 Parameter 5-5-5 5-5-5 Unit CL (IDD) 5 5 tCK tRCD (IDD) 12.5 15 ns tRC (IDD) 57.5 60 ns tRRD (IDD)- ×8 7.5 7.5 ns tRRD (IDD)- ×16 10 10 ns tFAW (IDD)- ×8 35 37.5 ns tFAW (IDD)- ×16 45 50 ns tCK (IDD) 2.5 3 ns tRAS (min.)(IDD) 45 45 ns tRAS (max.)(IDD) 70000 70000 ns tRP (IDD) 12.5 15 ns tRFC (IDD) 127.5 127.5 ns IDD7 Timing Patterns for 8 Banks The detailed timings are shown in the IDD7 Timing Patterns for 8 Banks tables. [ ×8 organization] Speed bins Timing Patterns DDR2-667 A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D DDR2-800 A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D [ ×16 organization] Speed bins Timing Patterns DDR2-667 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D DDR2-800 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D Remark: A = Active. RA = Read with auto precharge. D = Deselect Notes: 1. All banks are being interleaved at minimum tRC (IDD) without violating tRRD (IDD) and tFAW (IDD) using a Burst length = 4. 2. Control and address bus inputs are STABLE during DESELECTs. 3. IOUT = 0mA. |
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