EBE21FD4AHFT-6E-E datasheet(11/22 Pages) ELPIDA

Part #	EBE21FD4AHFT-6E-E

Description	2GB Fully Buffered DIMM

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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11 / 22 page

EBE21FD4AHFT, EBE21FD4AHFE, EBE21FD4AHFL

Preliminary Data Sheet E1001E30 (Ver. 3.0)

11

AMB Component Timing

For purposes of IDD testing, the following parameters are to be utilized.

Parameter

Symbol

min.

typ.

max.

Units

Note

EI Assertion pass-thru timing

tEI

propagate

—

4

clks

EI deassertion pass-thru timing

tEID

—

bit lock

clks

EI assertion duration

tEI

100

—

clks

Resample pass-thru time

—

TBD

—

ns

Resynch pass-thru Time

—

TBD

—

ns

Bit lock Interval

tBitLock

—

119

frames

Frame lock Interval

tFrameLock

—

154

frames

Note: 1. The EI stands for

″Electrical Idle″.

Power Specification Parameter and Test Conditions

-6E

-5C

Frequency (Mbps)

667

533

Parameter

Symbol

Power

Supply

max.

Unit

Conditions

Note

@1.5V

2.60

2.20

A

@1.8V

2.58

2.34

A

Idle Current,

single or last

DIMM

Idd_Idle_0

Total

8.14

7.05

W

L0 state, idle (0 BW)

Primary channel enabled,

Secondary channel disabled

CKE high. Command and address lines stable.

DRAM clock active.

@1.5V

3.40

3.00

A

@1.8V

2.57

2.33

A

Idle Current, first

DIMM

Idd_Idle_1

Total

9.37

8.30

W

L0 state, idle (0 BW)

Primary and secondary channels enabled

CKE high. Command and address lines stable.

DRAM clock active.

@1.5V

3.90

3.40

A

@1.8V

4.82

4.68

A

Active Power

Idd_Active_1

Total

14.44

13.39

W

L0 state

50% DRAM BW, 67% read, 33% write.

Primary and secondary channels enabled.

DRAM clock active, CKE high.

@1.5V

3.70

3.20

A

@1.8V

2.20

2.01

A

Active Power,

data pass through

Idd_Active_2

Total

9.14

8.01

W

L0 state

50% DRAM BW to downstream DIMM,

67% read, 33% write.

Primary and secondary channels enabled.

CKE high. Command and address lines stable.

DRAM clock active.

@1.5V

4.00

3.50

A

@1.8V

2.39

2.18

A

Training

Idd_Training

(for AMB spec.

Not in SPD)

Total

9.99

8.81

W

Primary and secondary channels enabled.

100% toggle on all channel lanes

DRAMs idle. 0 BW.

CKE high, Command and address lines stable.

DRAM clock active.

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