Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

EDE1108ACSE-5C-E Datasheet(PDF) 9 Page - Elpida Memory

Part # EDE1108ACSE-5C-E
Description  1G bits DDR2 SDRAM
Download  82 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EDE1108ACSE-5C-E Datasheet(HTML) 9 Page - Elpida Memory

Back Button EDE1108ACSE-5C-E Datasheet HTML 5Page - Elpida Memory EDE1108ACSE-5C-E Datasheet HTML 6Page - Elpida Memory EDE1108ACSE-5C-E Datasheet HTML 7Page - Elpida Memory EDE1108ACSE-5C-E Datasheet HTML 8Page - Elpida Memory EDE1108ACSE-5C-E Datasheet HTML 9Page - Elpida Memory EDE1108ACSE-5C-E Datasheet HTML 10Page - Elpida Memory EDE1108ACSE-5C-E Datasheet HTML 11Page - Elpida Memory EDE1108ACSE-5C-E Datasheet HTML 12Page - Elpida Memory EDE1108ACSE-5C-E Datasheet HTML 13Page - Elpida Memory Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 82 page
background image
EDE1104ACSE, EDE1108ACSE, EDE1116ACSE
Data Sheet E0975E50 (Ver.5.0)
9
max.
Parameter
Symbol
Grade
× 4
× 8
× 16
Unit
Test condition
Auto-refresh current
IDD5
-8E
-6E
-5C
290
280
270
290
280
270
290
280
270
mA
tCK = tCK (IDD);
Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self-refresh current
IDD6
-8E
-6E
-5C
10
10
10
10
10
10
10
10
10
mA
Self-Refresh Mode;
CK and /CK at 0V;
CKE
≤ 0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
Operating current
(Bank interleaving)
IDD7
-8E
-6E
-5C
290
275
260
290
275
260
350
310
290
mA
all bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD (IDD)
−1
× tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD),
tFAW = tFAW (IDD), tRCD = 1
× tCK (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS and /RDQS. IDD values must be met with all
combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN
≤ VIL (AC) (max.)
H is defined as VIN
≥ VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.


Similar Part No. - EDE1108ACSE-5C-E

ManufacturerPart #DatasheetDescription
logo
Elpida Memory
EDE1108ACBG ELPIDA-EDE1108ACBG Datasheet
816Kb / 82P
   1G bits DDR2 SDRAM
EDE1108ACBG-5C-E ELPIDA-EDE1108ACBG-5C-E Datasheet
816Kb / 82P
   1G bits DDR2 SDRAM
EDE1108ACBG-6E-E ELPIDA-EDE1108ACBG-6E-E Datasheet
816Kb / 82P
   1G bits DDR2 SDRAM
EDE1108ACBG-8E-E ELPIDA-EDE1108ACBG-8E-E Datasheet
816Kb / 82P
   1G bits DDR2 SDRAM
More results

Similar Description - EDE1108ACSE-5C-E

ManufacturerPart #DatasheetDescription
logo
Elpida Memory
EDE1104ACBG ELPIDA-EDE1104ACBG Datasheet
816Kb / 82P
   1G bits DDR2 SDRAM
EDE1116BEBG ELPIDA-EDE1116BEBG Datasheet
801Kb / 77P
   1G bits DDR2 SDRAM
EDE1108AESE ELPIDA-EDE1108AESE Datasheet
785Kb / 78P
   1G bits DDR2 SDRAM
EDE1108AJBG-1J-F ELPIDA-EDE1108AJBG-1J-F Datasheet
566Kb / 74P
   1G bits DDR2 SDRAM
EDE1104ABSE ELPIDA-EDE1104ABSE Datasheet
644Kb / 82P
   1G bits DDR2 SDRAM
EDE1108AEBG ELPIDA-EDE1108AEBG Datasheet
631Kb / 78P
   1G bits DDR2 SDRAM
EDE1108AJBG-1 ELPIDA-EDE1108AJBG-1 Datasheet
571Kb / 74P
   1G bits DDR2 SDRAM
EDE1108AFBG ELPIDA-EDE1108AFBG Datasheet
770Kb / 78P
   1G bits DDR2 SDRAM
EDE1104AFSE ELPIDA-EDE1104AFSE Datasheet
658Kb / 78P
   1G bits DDR2 SDRAM
EDE1108AJBG ELPIDA-EDE1108AJBG Datasheet
571Kb / 75P
   1G bits DDR2 SDRAM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com