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EDE1108ACSE-5C-E Datasheet(PDF) 9 Page - Elpida Memory |
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EDE1108ACSE-5C-E Datasheet(HTML) 9 Page - Elpida Memory |
9 / 82 page EDE1104ACSE, EDE1108ACSE, EDE1116ACSE Data Sheet E0975E50 (Ver.5.0) 9 max. Parameter Symbol Grade × 4 × 8 × 16 Unit Test condition Auto-refresh current IDD5 -8E -6E -5C 290 280 270 290 280 270 290 280 270 mA tCK = tCK (IDD); Refresh command at every tRFC (IDD) interval; CKE is H, /CS is H between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self-refresh current IDD6 -8E -6E -5C 10 10 10 10 10 10 10 10 10 mA Self-Refresh Mode; CK and /CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Operating current (Bank interleaving) IDD7 -8E -6E -5C 290 275 260 290 275 260 350 310 290 mA all bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD (IDD) −1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tFAW = tFAW (IDD), tRCD = 1 × tCK (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4W; Notes: 1. IDD specifications are tested after the device is properly initialized. 2. Input slew rate is specified by AC Input Test Condition. 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, /DQS, RDQS and /RDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD L is defined as VIN ≤ VIL (AC) (max.) H is defined as VIN ≥ VIH (AC) (min.) STABLE is defined as inputs stable at an H or L level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between H and L every other clock cycle (once per two clocks) for address and control signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals not including masks or strobes. 6. Refer to AC Timing for IDD Test Conditions. |
Similar Part No. - EDE1108ACSE-5C-E |
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Similar Description - EDE1108ACSE-5C-E |
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