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EBD11RD8ADFA Datasheet(PDF) 11 Page - Elpida Memory |
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EBD11RD8ADFA Datasheet(HTML) 11 Page - Elpida Memory |
11 / 19 page EBD11RD8ADFA Preliminary Data Sheet E0441E10 (Ver. 1.0) 11 DC Characteristics 1 (TA = 0 to +70°C, VDD = 2.5V ± 0.2V, VSS = 0V) Parameter Symbol Grade max. Unit Test condition Notes Operating current (ACTV-PRE) IDD0 -6B -7A, -7B 2395 2170 mA CKE ≥ VIH, tRC = tRC (min.) 1, 2, 9 Operating current (ACTV-READ-PRE) IDD1 -6B -7A, -7B 2845 2530 mA CKE ≥ VIH, BL = 4, CL = 3.5, tRC = tRC (min.) 1, 2, 5 Idle power down standby current IDD2P 514 mA CKE ≤ VIL 4 Floating idle standby current IDD2F -6B -7A, -7B 1000 910 mA CKE ≥ VIH, /CS ≥ VIH, DQ, DQS, DM = VREF 4, 5 Quiet idle standby current IDD2Q 820 mA CKE ≥ VIH, /CS ≥ VIH, DQ, DQS, DM = VREF 4, 10 Active power down standby current IDD3P 820 mA CKE ≤ VIL 3 Active standby current IDD3N -6B -7A, -7B 1630 1450 mA CKE ≥ VIH, /CS ≥ VIH tRAS = tRAS (max.) 3, 5, 6 Operating current (Burst read operation) IDD4R -6B -7A, -7B 3295 2845 mA CKE ≥ VIH, BL = 2, CL = 3.5 1, 2, 5, 6 Operating current (Burst write operation) IDD4W -6B -7A, -7B 3295 2845 mA CKE ≥ VIH, BL = 2, CL = 3.5 1, 2, 5, 6 Auto refresh current IDD5 -6B -7A, -7B 3925 3655 mA tRFC = tRFC (min.), Input ≤ VIL or ≥ VIH Self refresh current IDD6 532 mA Input ≥ VDD – 0.2 V Input ≤ 0.2 V Operating current (4 banks interleaving) IDD7A -6B -7A, -7B 5635 4825 mA BL = 4 1, 5, 6, 7 Notes. 1. These IDD data are measured under condition that DQ pins are not connected. 2. One bank operation. 3. One bank active. 4. All banks idle. 5. Command/Address transition once per one cycle. 6. DQ, DM, DQS transition twice per one cycle. 7. 4 banks active. Only one bank is running at tRC = tRC (min.) 8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general. 9. Command/Address transition once every two clock cycles. 10. Command/Address stable at ≥ VIH or ≤ VIL. DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V) (DDR SDRAM component Specification) Parameter Symbol min. max. Unit Test condition Notes Input leakage current ILI –2 2 µA VDD ≥ VIN ≥ VSS Output leakage current ILO –5 5 µA VDDQ ≥ VOUT ≥ VSS Output high current IOH –15.2 — mA VOUT = 1.95V Output low current IOL 15.2 — mA VOUT = 0.35V |
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