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EDE2516AASE-AE Datasheet(PDF) 8 Page - Elpida Memory |
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EDE2516AASE-AE Datasheet(HTML) 8 Page - Elpida Memory |
8 / 66 page EDE2508AASE/16AASE-DF, -BE, -AE Preliminary Data Sheet E0515E12 (Ver. 1.2) 8 max. Parameter Symbol Grade × 8 × 16 Unit Test condition -DF 270 270 -BE 270 270 Auto-refresh current IDD5 -AE 260 260 mA tCK = tCK (IDD); Refresh command at every tRFC (IDD) interval; CKE is H, /CS is H between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING 6 6 Self-refresh current IDD6 mA Self Refresh Mode; CK and /CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING -DF 340 475 -BE 340 475 Operating current (Bank interleaving) IDD7 -AE 330 460 mA all bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD (IDD) −1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD), tRCD = 1 × tCK (IDD); See Notes 7; CKE is H, CS is H between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4W; Notes: 1. IDD specifications are tested after the device is properly initialized. 2. Input slew rate is specified by AC Input Test Condition. 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD L is defined as VIN ≤ VIL (AC) (max.) H is defined as VIN ≥ VIH (AC) (min.) STABLE is defined as inputs stable at an H or L level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between H and L every other clock cycle (once per two clocks) for address and control signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals not including masks or strobes. 6. Refer to AC Timing for IDD Test Conditions. 7. In case of -DF (DDR2-700), tRCD must be 2 × tCK (IDD) and AL must be 4 × tCK (IDD) because AL = 5 is not supported in this device. AC Timing for IDD Test Conditions For purposes of IDD testing, the following parameters are to be utilized. DDR2-700 DDR2-667 DDR2-600 Parameter 5-6-6 5-5-5 5-5-5 Unit CL(IDD) 5 5 5 tCK tRCD(IDD) 15 15 15 ns tRC(IDD) 67.5 60 65 ns tRRD(IDD) 7.5 7.5 7.5 ns tCK(IDD) 2.85 3 3.3 ns tRAS(min.)(IDD) 50 45 47.5 ns tRAS(max.)(IDD) 70000 70000 70000 ns tRP(IDD) 15 15 15 ns tRFC(IDD) 85 75 80 ns |
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