EDE2516AASE-AE datasheet(8/66 Pages) ELPIDA

Part #	EDE2516AASE-AE

Description	256M bits DDR2 SDRAM for HYPER DIMM

Download	66 Pages

Scroll/Zoom	100%

Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

Logo

8 / 66 page

EDE2508AASE/16AASE-DF, -BE, -AE

Preliminary Data Sheet E0515E12 (Ver. 1.2)

8

max.

Parameter

Symbol

Grade

× 8

× 16

Unit

Test condition

-DF

270

-BE

270

Auto-refresh current

IDD5

-AE

260

mA

tCK = tCK (IDD);

Refresh command at every tRFC (IDD) interval;

CKE is H, /CS is H between valid commands;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

6

Self-refresh current

IDD6

mA

Self Refresh Mode;

CK and /CK at 0V;

CKE

≤ 0.2V;

Other control and address bus inputs are FLOATING;

Data bus inputs are FLOATING

-DF

340

475

-BE

340

475

Operating current

(Bank interleaving)

IDD7

-AE

330

460

mA

all bank interleaving reads, IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = tRCD (IDD)

−1

× tCK (IDD);

tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),

tRCD = 1

× tCK (IDD); See Notes 7;

CKE is H, CS is H between valid commands;

Address bus inputs are STABLE during DESELECTs;

Data pattern is same as IDD4W;

Notes: 1. IDD specifications are tested after the device is properly initialized.

2. Input slew rate is specified by AC Input Test Condition.

3. IDD parameters are specified with ODT disabled.

4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD

values must be met with all combinations of EMRS bits 10 and 11.

5. Definitions for IDD

L is defined as VIN

≤ VIL (AC) (max.)

H is defined as VIN

≥ VIH (AC) (min.)

STABLE is defined as inputs stable at an H or L level

FLOATING is defined as inputs at VREF = VDDQ/2

SWITCHING is defined as:

inputs changing between H and L every other clock cycle (once per two clocks) for address and control

signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals

not including masks or strobes.

6. Refer to AC Timing for IDD Test Conditions.

7. In case of -DF (DDR2-700), tRCD must be 2

× tCK (IDD) and AL must be 4 × tCK (IDD) because AL = 5 is

not supported in this device.

AC Timing for IDD Test Conditions

For purposes of IDD testing, the following parameters are to be utilized.

DDR2-700

DDR2-667

DDR2-600

Parameter

5-6-6

5-5-5

Unit

CL(IDD)

5

tCK

tRCD(IDD)

15

ns

tRC(IDD)

67.5

60

65

ns

tRRD(IDD)

7.5

ns

tCK(IDD)

2.85

3

3.3

ns

tRAS(min.)(IDD)

50

45

47.5

ns

tRAS(max.)(IDD)

70000

ns

tRP(IDD)

15

ns

tRFC(IDD)

85

75

80

ns

Similar Part No. - EDE2516AASE-AE

Manufacturer	Part #	Datasheet	Description
Elpida Memory	EDE2516AASE-4A-E	706Kb / 66P	256M bits DDR2 SDRAM
	EDE2516AASE-4C-E	706Kb / 66P	256M bits DDR2 SDRAM
	EDE2516AASE-5C-E	706Kb / 66P	256M bits DDR2 SDRAM
	EDE2516AASE-6E-E	706Kb / 66P	256M bits DDR2 SDRAM

More results

Similar Description - EDE2516AASE-AE

Manufacturer	Part #	Datasheet	Description
Elpida Memory	EDE2508ABSE-GE	707Kb / 66P	256M bits DDR2 SDRAM for HYPER DIMM
	EDE5108ABSE-BE	700Kb / 65P	512M bits DDR2 SDRAM for HYPER DIMM
	EDE2508AEBG	625Kb / 77P	256M bits DDR2 SDRAM
	EDE2504AASE	706Kb / 66P	256M bits DDR2 SDRAM
	EDE2508ABSE	708Kb / 66P	256M bits DDR2 SDRAM
	EDE2508ACSE	881Kb / 81P	256M bits DDR2 SDRAM
	EBE11UD8ABFV	203Kb / 22P	1GB Unbuffered DDR2 SDRAM DIMM HYPER DIMM?
	EBE25UC8AAFV	238Kb / 22P	256MB Unbuffered DDR2 SDRAM HYPER DIMM?
	EBE52UC8AAFV	205Kb / 22P	512MB Unbuffered DDR2 SDRAM HYPER DIMM?
	EBE51UD8ABFV	236Kb / 22P	512MB Unbuffered DDR2 SDRAM HYPER DIMM?

More results

EDE2516AASE-AE Datasheet(PDF) 8 Page - Elpida Memory

EDE2516AASE-AE Datasheet(HTML) 8 Page - Elpida Memory

Similar Part No. - EDE2516AASE-AE

Similar Description - EDE2516AASE-AE

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

Datasheet Download

Link URL