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EBR12EC8ABSA Datasheet(PDF) 3 Page - Elpida Memory |
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EBR12EC8ABSA Datasheet(HTML) 3 Page - Elpida Memory |
3 / 11 page EBR12EC8ABSA Preliminary Data Sheet E0321E11 (Ver. 1.1) 3 Pad Signal Name Pad Signal Name Pad Signal Name Pad Signal Name A37 GND B37 GND A77 RDQA5 B77 RDQA6 A38 NC B38 NC A78 GND B78 GND A39 VCMOS B39 VCMOS A79 RDQA7 B79 RDQA8 A40 NC B40 NC A80 GND B80 GND Module Connector Pad Description Signal Module Connector Pads I/O Type Description GND A1, A3, A5, A7, A9, A11, A13, A15, A17, A19, A21, A23, A25, A27, A29,A31, A33, A37, A48, A50, A52, A54,A56, A58, A60, A62, A64, A66, A68,A70, A72, A74, A76, A78, A80, B1,B3, B5, B7, B9, B11, B13, B15, B17,B19, B21, B23, B25, B27, B29, B31,B33, B37, B48, B50, B52, B54, B56, B58, B60, B62, B64, B66, B68, B70, B72, B74, B76, B78, B80 – – Ground reference for RDRAM core and interface. LCFM B10 I RSL Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. LCFMN B12 I RSL Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity. LCMD B32 I VCMOS Serial Command used to read from and write to the control registers. Also used for power management. LCOL4..LCOL0 A18, B18, A20, B20, A22 I RSL Column bus. 5-bit bus containing control and address information for column accesses. LCTM A12 I RSL Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. LCTMN A14 I RSL Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. LDQA8..LDQA0 A2, B2, A4, B4, A6, B6, A8, B8, A10 I/O RSL Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM.. LDQB8..LDQB0 B30, B28, A30, B26, A28, B24, A26, B22, A24 I/O RSL Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM. LROW2..LROW0 B14, A16, B16 I RSL Row bus. 3-bit bus containing control and address information for row accesses. LSCK A32 I VCMOS Serial clock input. Clock source used to read from and write to the RDRAM control registers. NC A36, B36, A38, B38, A40, B40, A41, B41 – – These pads are not connected. These 8 connector pads are reserved for future use. RCFM A71 I RSL Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. RCFMN A69 I RSL Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity. RCMD B49 I VCMOS Serial Command Input used to read from and write to the control registers. Also used for power management. RCOL4..RCOL0 B63, A63, B61, A61, B59 I RSL Column bus. 5-bit bus containing control and address information for column accesses. RCTM B69 I RSL Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. RCTMN B67 I RSL Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. |
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