EBD51RD8ABFA

Preliminary Data Sheet E0376E10 (Ver. 1.0)

9

Differential Clock Net Wiring (CK0, /CK0)

120

Ω

240

Ω

(Typically two registers per DIMM)

0ns (nominal)

240

Ω

120

Ω

120

Ω

CK0

Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register will

be set to 0 ns (nominal).

2. Input, output and feedback clock lines are terminated from line to line as shown, and not

from line to ground.

3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired

in a similar manner.

4. Termination resistors for feedback path clocks are located after the pins of the PLL.

5. SDRAM clock pair inputs have a parallel capacitor equal to one-half nominal SDRAM

input clock load.

C

/CK0

SDRAM

Register1

Register2

PLL

Feedback

IN

OUT1

OUT'N'

Capacitance