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EBR25EC8ABSA Datasheet(PDF) 7 Page - Elpida Memory |
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EBR25EC8ABSA Datasheet(HTML) 7 Page - Elpida Memory |
7 / 11 page EBR25EC8ABSA Preliminary Data Sheet E0320E11 (Ver. 1.1) 7 AC Electrical Specifications Symbol Parameter and Conditions Grade min. typ. max. Unit Z Module Impedance of RSL signals 25.2 28.0 30.8 Ω Module Impedance of SCK and CMD signals 23.8 28.0 32.2 Ω TPD Average clock delay from finger to finger of all RSL clock nets (CTM, CTMN,CFM, and CFMN) — — TBD ns ∆TPD Propagation delay variation of RSL signals with respect to TPD * 1, 2 TBD — TBD ps ∆TPD-CMOS Propagation delay variation of SCK signal with respect to an average clock delay * 1 TBD — TBD ps ∆TPD- SCK,CMD Propagation delay variation of CMD signal with respect to SCK signal TBD — TBD ps V α/VIN Attenuation Limit -AD -8C — — TBD % VXF/VIN Forward crosstalk coefficient (300ps input rise time 20% - 80%) -AD -8C — — TBD % VXB/VIN Backward crosstalk coefficient (300ps input rise time 20% - 80%) -AD -8C — — TBD % RDC DC Resistance Limit -AD -8C — — TBD Ω Notes 1. TPD or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM, CTMN, CFM, and CFMN). 2. If the SO-RIMM module meets the following specification, then it is compliant to the specification. If the SO-RIMM module does not meet these specifications, then the specification can be adjusted by the “Adjusted ∆TPD Specification” table. Adjusted ∆TPD Specification Absolute Symbol Parameter and conditions Adjusted min./max. min. max. Unit ∆TPD Propagation delay variation of RSL signals with respect to TPD +/ − [17+(18*N*∆Z0)] *1 TBD TBD ps Note: 1 N = Number of RDRAM devices installed on the SO-RIMM module. ∆Z0 = delta Z0% = (max. Z0 - min. Z0) / (min. Z0) (max. Z0 and min. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers on the module.) |
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