HM5212165FTD-A60 datasheet(9/62 Pages) ELPIDA

Part #	HM5212165FTD-A60

Description	128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword 횞 16-bit 횞 4-bank/4-Mword 횞 8-bit 횞 4-bank PC/133, PC/100 SDRAM

Download	62 Pages

Scroll/Zoom	100%

Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

Logo

9 / 62 page

HM5212165FTD/HM5212805FTD-75/A60/B60

Data Sheet E0179H10

9

Column address strobe and write command [WRIT]: This command starts a write operation. When the

burst write mode is selected, the column address (AY0 to AY8; HM5212165F, AY0 to AY9; HM5212805F)

and the bank select address (A12/A13) become the burst write start address. When the single write mode is

selected, data is only written to the location specified by the column address (AY0 to AY8; HM5212165F, AY0

to AY9; HM5212805F) and the bank select address (A12/A13).

Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation after a

burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is full-page, this

command is illegal.

Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by

A12/A13 (BS) and determines the row address (AX0 to AX11). When A12 and A13 are Low, bank 0 is

activated. When A12 is High and A13 is Low, bank 1 is activated. When A12 is Low and A13 is High, bank 2

is activated. When A12 and A13 are High, bank 3 is activated.

Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by A12/A13.

If A12 and A13 are Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low

and A13 is High, bank 2 is selected. If A12 and A13 are High, bank 3 is selected.

Precharge all banks [PALL]: This command starts a precharge operation for all banks.

Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation, the

one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section.

Mode register set [MRS]: The SDRAM has a mode register that defines how it operates. The mode register is

specified by the address pins (A0 to A13) at the mode register set cycle. For details, refer to the mode register

configuration. After power on, the contents of the mode register are undefined, execute the mode register set

command to set up the mode register.

Similar Part No. - HM5212165FTD-A60

Manufacturer	Part #	Datasheet	Description
Hitachi Semiconductor	HM5212165FTD-A60	859Kb / 63P	128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM

More results

Similar Description - HM5212165FTD-A60

Manufacturer	Part #	Datasheet	Description
Elpida Memory	HM5212165FLTD-75	645Kb / 62P	128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword 횞 16-bit 횞 4-bank/4-Mword 횞 8-bit 횞 4-bank PC/133, PC/100 SDRAM
	HM5225165B	462Kb / 63P	256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 횞 16-bit 횞 4-bank/8-Mword 횞 8-bit 횞 4-bank /16-Mword 횞 4-bit 횞 4-bank PC/133, PC/100 SDRAM
	HM5257165B	463Kb / 62P	512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 횞 16-bit 횞 4-bank/16-Mword 횞 8-bit 횞 4-bank /32-Mword 횞 4-bit 횞 4-bank PC/133, PC/100 SDRAM
	HM5259165B	368Kb / 63P	512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 횞 16-bit 횞 4-bank/16-Mword 횞 8-bit 횞 4-bank /32-Mword 횞 4-bit 횞 4-bank PC/133, PC/100 SDRAM
	HM5264165F-75	514Kb / 65P	64M LVTTL interface SDRAM 133 MHz/100 MHz 1-Mword 횞 16-bit 횞 4-bank/2-Mword 횞 8-bit 횞 4-bank /4-Mword 횞 4-bit 횞 4-bank PC/133, PC/100 SDRAM
	HM5425161B	489Kb / 65P	256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 횞 16-bit 횞 4-bank/8-Mword 횞 8-bit 횞 4-bank/ 16-Mword 횞 4-bit 횞 4-bank
	HM52Y25165B-B6	363Kb / 60P	256M SDRAM 100 MHz 4-Mword 횞 16-bit 횞 4-bank /16-Mword 횞 4-bit 횞 4-bank
Hitachi Semiconductor	HM5212165F	859Kb / 63P	128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM
	HM5212325F	62Kb / 13P	128M LVTTL interface SDRAM 100 MHz 1-Mword x 32-bit x 4-bank PC/100 SDRAM
	HM5212325FBPC	58Kb / 13P	128M LVTTL interface SDRAM 100 MHz 1-Mword x 32-bit x 4-bank PC/100 SDRAM

More results

HM5212165FTD-A60 Datasheet(PDF) 9 Page - Elpida Memory

HM5212165FTD-A60 Datasheet(HTML) 9 Page - Elpida Memory

Similar Part No. - HM5212165FTD-A60

Similar Description - HM5212165FTD-A60

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Datasheet Download

Link URL