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HB54A2569F1-10B Datasheet(PDF) 10 Page - Elpida Memory |
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HB54A2569F1-10B Datasheet(HTML) 10 Page - Elpida Memory |
10 / 17 page HB54A2569F1, HB54A5129F2 Data Sheet E0091H40 (Ver. 4.0) 10 Differential Clock Net Wiring (CK0, /CK0) 120 Ω 240 Ω (Typically two registers per DIMM) 0ns (nominal) 240 Ω 120 Ω 120 Ω CK0 Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl be set to 0 ns (nominal). 2. Input, output and feedback clock lines are terminated from line to line as shown, and not from line to ground. 3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner. 4. Termination resistors for feedback path clocks are located after the pins of the PLL. C /CK0 SDRAM stack SDRAM stack Register1 Register2 PLL Feedback IN OUT1 OUT'N' |
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