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HM5164165FTT-5 Datasheet(PDF) 7 Page - Elpida Memory |
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HM5164165FTT-5 Datasheet(HTML) 7 Page - Elpida Memory |
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7 / 36 page  HM5164165F Series, HM5165165F Series Data Sheet E0099H10 7 Operation Table RAS LCAS UCAS WE OE I/O 0 to I/O 7 I/O 8 to I/O 15 Operation H ×××× High-Z High-Z Standby L L H H L Dout High-Z Read cycle L H L H L High-Z Dout LLLH L Dout Dout LLH L* 2 × Din × Early write cycle LH LL* 2 ×× Din LLLL* 2 × Din Din LLH L* 2 H Din × Delayed write cycle LH LL* 2 H × Din LLLL* 2 H Din Din L L H H to L L to H Dout/Din High-Z Read-modify-write cycle L H L H to L L to H High-Z Dout/Din LLLH to L L to H Dout/Din Dout/Din LH H ×× High-Z High-Z RAS-only refresh cycle H to L H L H × High-Z High-Z CAS-before-RAS refresh cycle or H to L L H H × High-Z High-Z Self refresh cycle (L-version) H to L L L H × High-Z High-Z L L L H H High-Z High-Z Read cycle (Output disabled) Notes: 1. H: V IH (inactive) L: V IL (active) ×: V IH or VIL 2. t WCS ≥ 0 ns: Early write cycle t WCS < 0 ns: Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliestof UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write operation and output High-Z control are done independently by each UCAS, LCAS. ex. if RAS = H to L, LCAS = L, UCAS = H, then CAS-before-RAS refresh cycle is selected. |
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