EDD2508AJTA-7A datasheet(5/50 Pages) ELPIDA

Part #	EDD2508AJTA-7A

Description	256M bits DDR SDRAM

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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5 / 50 page

EDD2504AJTA, EDD2508AJTA

Preliminary Data Sheet E0145E50 (Ver. 5.0)

5

DC Characteristics 1 (TA = 0 to +70

°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)

max.

Parameter

Symbol

Grade

× 4

× 8

Unit

Test condition

Notes

Operating current (ACT-PRE) IDD0

-6B

-7A, -7B

120

110

120

110

mA

CKE ≥ VIH,

tRC = tRC (min.)

1, 2, 9

Operating current

(ACT-READ-PRE)

IDD1

-6B

-7A, -7B

150

140

150

140

mA

CKE ≥ VIH, BL = 4,

CL = 2.5,

tRC = tRC (min.)

1, 2, 5

Idle power down standby

current

IDD2P

3

mA

CKE ≤ VIL

4

Floating idle standby current IDD2F

-6B

-7A, -7B

35

30

35

30

mA

CKE ≥ VIH, /CS ≥ VIH

DQ, DQS, DM = VREF

4, 5

Quiet idle standby current

IDD2Q

-6B

-7A, -7B

30

25

30

25

mA

CKE ≥ VIH, /CS ≥ VIH

DQ, DQS, DM = VREF

4, 10

Active power down standby

current

IDD3P

20

mA

CKE ≤ VIL

3

Active standby current

IDD3N

-6B

-7A, -7B

55

50

55

50

mA

CKE ≥ VIH, /CS ≥ VIH

tRAS = tRAS (max.)

3, 5, 6

Operating current

(Burst read operation)

IDD4R

-6B

-7A, -7B

195

170

205

180

mA

CKE ≥ VIH, BL = 2,

CL = 2.5

1, 2, 5,

6

Operating current

(Burst write operation)

IDD4W

-6B

-7A, -7B

195

170

205

180

mA

CKE ≥ VIH, BL = 2,

CL = 2.5

1, 2, 5,

6

Auto Refresh current

IDD5

-6B

-7A, -7B

250

225

250

225

mA

tRFC = tRFC (min.),

Input ≤ VIL or ≥ VIH

Self refresh current

IDD6

3

mA

Input ≥ VDD – 0.2 V

Input ≤ 0.2 V

Operating current

(4 banks interleaving)

IDD7A

-6B

-7A, -7B

350

320

360

330

mA

BL = 4

5, 6, 7

Notes: 1. These IDD data are measured under condition that DQ pins are not connected.

2. One bank operation.

3. One bank active.

4. All banks idle.

5. Command/Address transition once per one clock cycle.

6. DQ, DM and DQS transition twice per one clock cycle.

7. 4 banks active. Only one bank is running at tRC = tRC (min.)

8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.

9. Command/Address transition once every two clock cycle.

10. Command/Address stable at ≥ VIH or ≤ VIL.

DC Characteristics 2 (TA = 0 to +70

°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)

Parameter

Symbol

min.

max.

Unit

Test condition

Notes

Input leakage current

ILI

–2

2

µA

VDD ≥ VIN ≥ VSS

Output leakage current

ILO

–5

5

µA

VDDQ ≥ VOUT ≥ VSS

Output high current

IOH

–15.2

—

mA

VOUT = 1.95V

Output low current

IOL

15.2

—

mA

VOUT = 0.35V

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