Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

HM5264405F-A60 Datasheet(PDF) 11 Page - Elpida Memory

Part # HM5264405F-A60
Description  64M LVTTL interface SDRAM 133 MHz/100 MHz 1-Mword16-bit4-bank/2-Mword8-bit4-bank /4-Mword4-bit4-bank PC/133, PC/100 SDRAM
Download  65 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

HM5264405F-A60 Datasheet(HTML) 11 Page - Elpida Memory

Back Button HM5264405F-A60 Datasheet HTML 7Page - Elpida Memory HM5264405F-A60 Datasheet HTML 8Page - Elpida Memory HM5264405F-A60 Datasheet HTML 9Page - Elpida Memory HM5264405F-A60 Datasheet HTML 10Page - Elpida Memory HM5264405F-A60 Datasheet HTML 11Page - Elpida Memory HM5264405F-A60 Datasheet HTML 12Page - Elpida Memory HM5264405F-A60 Datasheet HTML 13Page - Elpida Memory HM5264405F-A60 Datasheet HTML 14Page - Elpida Memory HM5264405F-A60 Datasheet HTML 15Page - Elpida Memory Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 65 page
background image
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
Data Sheet E0135H10
11
Column address strobe and read command [READ]: This command starts a read operation. In addition,
the start address of burst read is determined by the column address (AY0 to AY7; HM5264165F, AY0 to
AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select address (BS). After the read operation,
the output buffer becomes High-Z.
Read with auto-precharge [READ A]: This command automatically performs a precharge operation after a
burst read with a burst length of 1, 2, 4 or 8. When the burst length is full-page, this command is illegal.
Column address strobe and write command [WRIT]: This command starts a write operation. When the
burst write mode is selected, the column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F,
AY0 to AY9; HM5264405F) and the bank select address (A12/A13) become the burst write start address.
When the single write mode is selected, data is only written to the location specified by the column address
(AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select
address (A12/A13).
Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation after a
burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is full-page,
this command is illegal.
Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by
A12/A13 (BS) and determines the row address (AX0 to AX11). When A12 and A13 are Low, bank 0 is
activated. When A12 is High and A13 is Low, bank 1 is activated. When A12 is Low and A13 is High, bank
2 is activated. When A12 and A13 are High, bank 3 is activated.
Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by
A12/A13. If A12 and A13 are Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If
A12 is Low and A13 is High, bank 2 is selected. If A12 and A13 are High, bank 3 is selected.
Precharge all banks [PALL]: This command starts a precharge operation for all banks.
Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation,
the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section.
Mode register set [MRS]: The SDRAM has a mode register that defines how it operates. The mode register
is specified by the address pins (A0 to A13) at the mode register set cycle. For details, refer to the mode
register configuration. After power on, the contents of the mode register are undefined, execute the mode
register set command to set up the mode register.


Similar Part No. - HM5264405F-A60

ManufacturerPart #DatasheetDescription
logo
Hitachi Semiconductor
HM5264405F HITACHI-HM5264405F Datasheet
870Kb / 67P
   64M LVTTL interface SDRAM 133 MHz/100 MHz
HM5264405FLTT-75 HITACHI-HM5264405FLTT-75 Datasheet
870Kb / 67P
   64M LVTTL interface SDRAM 133 MHz/100 MHz
HM5264405FLTT-A60 HITACHI-HM5264405FLTT-A60 Datasheet
870Kb / 67P
   64M LVTTL interface SDRAM 133 MHz/100 MHz
HM5264405FLTT-B60 HITACHI-HM5264405FLTT-B60 Datasheet
870Kb / 67P
   64M LVTTL interface SDRAM 133 MHz/100 MHz
HM5264405FTT-75 HITACHI-HM5264405FTT-75 Datasheet
870Kb / 67P
   64M LVTTL interface SDRAM 133 MHz/100 MHz
More results

Similar Description - HM5264405F-A60

ManufacturerPart #DatasheetDescription
logo
Elpida Memory
HM5225165B ELPIDA-HM5225165B Datasheet
462Kb / 63P
   256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 횞 16-bit 횞 4-bank/8-Mword 횞 8-bit 횞 4-bank /16-Mword 횞 4-bit 횞 4-bank PC/133, PC/100 SDRAM
HM5257165B ELPIDA-HM5257165B Datasheet
463Kb / 62P
   512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 횞 16-bit 횞 4-bank/16-Mword 횞 8-bit 횞 4-bank /32-Mword 횞 4-bit 횞 4-bank PC/133, PC/100 SDRAM
HM5259165B ELPIDA-HM5259165B Datasheet
368Kb / 63P
   512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 횞 16-bit 횞 4-bank/16-Mword 횞 8-bit 횞 4-bank /32-Mword 횞 4-bit 횞 4-bank PC/133, PC/100 SDRAM
HM5212165FLTD-75 ELPIDA-HM5212165FLTD-75 Datasheet
645Kb / 62P
   128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword 횞 16-bit 횞 4-bank/4-Mword 횞 8-bit 횞 4-bank PC/133, PC/100 SDRAM
HM5212165FTD-75 ELPIDA-HM5212165FTD-75 Datasheet
570Kb / 62P
   128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword 횞 16-bit 횞 4-bank/4-Mword 횞 8-bit 횞 4-bank PC/133, PC/100 SDRAM
HM52Y25165B-B6 ELPIDA-HM52Y25165B-B6 Datasheet
363Kb / 60P
   256M SDRAM 100 MHz 4-Mword 횞 16-bit 횞 4-bank /16-Mword 횞 4-bit 횞 4-bank
HM5425161B ELPIDA-HM5425161B Datasheet
489Kb / 65P
   256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 횞 16-bit 횞 4-bank/8-Mword 횞 8-bit 횞 4-bank/ 16-Mword 횞 4-bit 횞 4-bank
logo
Hitachi Semiconductor
HM5212165F HITACHI-HM5212165F Datasheet
859Kb / 63P
   128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM
HM5225645F HITACHI-HM5225645F Datasheet
81Kb / 16P
   256M LVTTL interface SDRAM 100 MHz 1-Mword x 64-bit x 4-bank/2-Mword x 32-bit x 4-bank PC/100 SDRAM
logo
Elpida Memory
HB52F168GB-B ELPIDA-HB52F168GB-B Datasheet
135Kb / 19P
   128 MB Unbuffered SDRAM Micro DIMM 16-Mword 횞 64-bit, 133/100 MHz Memory Bus, 1-Bank Module (4 pcs of 16 M 횞 16 components) PC133/100 SDRAM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com