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HM5316123BF-10 Datasheet(PDF) 6 Page - Elpida Memory |
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HM5316123BF-10 Datasheet(HTML) 6 Page - Elpida Memory |
6 / 50 page 6 HM5316123B Series CAS (input pin): Column address and DSF1 signals are fetched into chip at the falling edge of CAS, which determines the operation mode of the HM5316123B. CAS controls output impedance of I/O in RAM. A0 – A8 (input pins): Row address (AX0 – AX8) is determined by A0 – A8 level at the falling edge of RAS. Column address (AY0 – AY7) is determined by A0 – A7 level at the falling edge of CAS. In transfer cycles, row address is the address on the word line which transfers data with SAM data register, and column address is the SAM start address after transfer. WEU and WEL (Input pins): WEU and WEL pins have two functions at the falling edge of RAS and after. When either WEU or WEL is low at the falling edge of RAS, the HM5316123B turns to mask write mode. According to the I/O level at the time, write on each I/O can be masked. ( WEU and WEL levels at the falling edge of RAS is don’t care in read cycle.) When both WEU and WEL are high at the falling edge of RAS, a no mask write cycle is executed. After that, WEU and WEL switch read/write cycles. Both WEU and WEL must be held high in a read cycle. In a transfer cycle, the direction of transfer is determined by WEU and WEL levels at the falling edge of RAS. When either WEU or WEL is low, data is transferred from SAM to RAM (data is written into RAM), and when both WEU and WEL are high, data is transferred from RAM to SAM (data is read from RAM). I/O0 – I/O15 (input/output pins): I/O pins function as mask data at the falling edge of RAS (in mask write mode). Data is written only to high I/O pins. Data on low I/O pins are masked and internal data are retained. After that, they function as inut/output pins as those of a standard DRAM. In block write cycle, they function as column mask data at the falling edges of CAS, and WEU or WEL. DT/OE (input pin): DT/OE pin functions as DT (data transfer) pin at the falling edge of RAS and as OE (output enable) pin after that. When DT is low at the falling edge of RAS, this cycle becomes a transfer cycle. When DT is high at the falling edge of RAS, RAM and SAM operate independently. SC (input pin): SC is a basic SAM clock. In a serial read cycle, data outputs from an SI/O pin synchronously with the rising edge of SC. In a serial write cycle, data on an SI/O pin at the rising edge of SC is fetched into the SAM data register. SE (input pin): SE pin activates SAM. When SE is high, SI/O is in the high impedance state in serial read cycle and data on SI/O is not fetched into the SAM data register in serial write cycle. SE can be used as a mask for serial write because the internal pointer is incremented at the rising edge of SC. SI/O0 – SI/O15 (input/output pins): SI/Os are input/output pins in SAM. Direction of input/output is determined by the previous transfer cycle. When it was a read transfer cycle, SI/O outputs data. When it was a masked write transfer cycle, SI/O inputs data. DSF1 (input pin): DSF1 is a special function data input flag pin. It is set to high at the falling edge of RAS when new functions such as color register and mask register read/write, split transfer, and flash write, are used. DSF2 (input pin): DSF2 is also a special function data input flag pin. This pin is fixed to low level in all operations of the HM5316123B. QSF (output pin): QSF outputs data of address A7 in SAM. QSF is switched from low to high by accessing address 127 in SAM and from high to low by accessing address 255 in SAM. Preliminary Data Sheet E0160H10 |
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