HM5316123BF-10 datasheet(8/50 Pages) ELPIDA

Part #	HM5316123BF-10

Description	131,072-word x 16-bit Multiport CMOS Video RAM

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Manufacturer	ELPIDA [Elpida Memory]

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HM5316123B Series

Color Register Set/Read Cycle (

CAS high,

DT/OE high, WEU and WEL high and DSF1 high

at the falling edge of

RAS)

In color register set cycle, color data is set to the

internal color register used in flash write cycle or

block write cycle. 16 bits of internal color register

are provided at each I/O.

This register is

composed of static circuits, so once it is set, it

retains the data until reset. Since color register set

cycle is just as same as the usual write cycle, so

read, early write and delayed write cycle can be

executed.

In this cycle, the HM5316123B

refreshes the row address fetched at the falling

edge of

RAS.

Mask Register Set/Read Cycle (

CAS high,

DT/OE high, WEU and WEL high, and DSF1 high

at the falling edge of

RAS)

In mask register set cycle, mask data is set to the

internal mask register used in mask write cycle,

block write cycle, flash write cycle, masked write

transfer, and masked split write transfer. 16 bits of

internal mask register are provided at each I/O.

This mask register is composed of static circuits,

so once it is set, it retains the data until reset.

Since mask register set cycle is just as same as the

usual read and write cycle, so read, early and

delayed write cycles can be executed.

Flash Write Cycle (

CAS high, DT/OE high, WEU

or

WEL low, and DSF1 high at the falling edge of

RAS)

In a flash write cycle, a row of data (256 word x 16

bit) is cleared to 0 or 1 at each I/O according to the

data of color register mentioned before. It is also

necessary to mask I/O in this cycle. When

CAS

and

DT/OE is set high, WEU or WEL is low, and

DSF1 is high at the falling edge of

RAS, this cycle

starts. Then, the row address to clear is given to

row address. Mask data is as same as that of a

RAM write cycle.

Cycle time is the same as

those of RAM read/write cycles, so all bits can be

cleared in 1/256 of the usual cycle time. (See

figure 1.)

RAS

CAS

Address

WEU,WEL

DT/OE

DSF1

I/O

Color Register Set Cycle

Flash Write Cycle

Row

Xi

Xj

*1

Color Data

Set color register

Execute flash write into each

I/O on row address Xi using

color register.

Execute flash write into

each I/O on row address

Xj using color register.

Note: 1. I/O Mask Data (In new mask mode)

Low: Mask

High: Non Mask

In persistent mask mode, I/O don't care

Figure 1 Use of Flash Write

Preliminary Data Sheet E0160H10

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HM5316123BF-10 Datasheet(PDF) 8 Page - Elpida Memory

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