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HM538254BTT-10 Datasheet(PDF) 10 Page - Elpida Memory |
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HM538254BTT-10 Datasheet(HTML) 10 Page - Elpida Memory |
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10 / 56 page  HM538253B/HM538254B Series Data Sheet E0163H10 10 same as the usual read and write cycle, so read, early write, and delayed write cycle can be executed. In this cycle, the HM538253B/ HM538254B refreshes the row address fetched at the falling edge of RAS. Mask Register Set/Read Cycle ( CAS high, DT/OE high, WE high, and DSF1 low at the falling edge of RAS: Mnemonic Code; LMR) In this cycle, mask data is set to the internal mask register persistently used in mask write cycle, block write cycle, flash write cycle, masked write transfer, and masked split write transfer. 8 bits of internal mask register are provided at each I/O. This mask register is composed of static circuits. So once it is reset by CBRR cycle, it retains the data until reset or reselect. Once LMR is set, mask write cycle data is written by persistent mask data. Since mask register set cycle is just the same as the usual read and write cycle, so read, early write, and delayed write cycle can be executed. Flash Write Cycle ( CAS high, DT/OE high, WE low, and DSF1 high at the falling edge of RAS: Mnemonic; FW) In a flash write cycle, a row of data (512 word × 8 bit) is cleared to 0 or 1 at each I/O according to the data in the color register mentioned before. It is also necessary to mask I/O in this cycle. When CAS and DT/OE are set high, WE is low, and DSF1 is high at the falling edge of RAS, this cycle starts. Then, the row address to clear is given to row address. Mask data is the same as that of a RAM write cycle. Cycle time is the same as those of RAM read/write cycles, so all bits can be cleared in 1/512 of the usual cycle time. (See figure 1.) Block Write Cycle ( CAS high, DT/OE high and DSF1 low at the falling edge of RAS, DSF1 high and WE low at the falling edge of CAS: Mnemonic; BW) In a block write cycle, 4 columns of data (4 column × 8 bit) are cleared to 0 or 1 at each I/O according to the data of color register. Column addresses A0 and A1 are disregarded. The mask data on I/Os and the mask data on column address can be determined independently. I/O level at the falling edge of CAS determines the address to be cleared. (See figure 2.) The block write cycle is as the same as the usual write cycle, so early and delayed write, read-modify-write, and page mode write cycle can be executed. No Mask Mode Block Write Cycle ( WE high at the falling edge of RAS): The data on 8 I/Os are all cleared when WE is high at the falling edge of RAS. Mask Block Write Cycle ( WE low at the falling edge of RAS):When WE is low at the falling edge of RAS, the HM538253B/HM538254B starts mask block write cycle to clear the data on an optional I/O. The mask data is the same as that of a RAM write cycle. High I/O is cleared, low I/O is not cleared and the internal data is retained. In new mask mode, the mask data is available in the RAS cycle. In persistent mask mode, I/O does not care about mask mode. |
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