5

M68000 USER’S MANUAL ADDENDUM

MOTOROLA

low-power mode described below will be routinely tested as part of the MC68SEC000 test vectors provided

by Motorola.

To successfully enter the low-power mode, the MC68SEC000 must first be in the supervisor mode. A

recommended method for entering the low-power mode is to use the TRAP instruction, which causes the

processor to begin exception processing, thus entering the supervisor mode. External circuitry should

accomplish the following steps during the trap routine:

1.

Externally detect a write to the low-power address. You select this address which can be any address

in the 16 Mbyte addressing range of the MC68SEC000. A write to the low-power address can be

detected by polling A23–A0, R/W, and FC2–FC0. When the low-power address is detected, R/W is

a logic low, and the function codes have a five (101) on their output, the processor is writing to the

low-power address in supervisor mode and user-designed circuitry should assert the

ADDRESS_MATCH signal shown in Figure 2 and Figure 3.

Figure 3. MC68SEC000 Low-Power Circuitry for 8-Bit Data Bus

2.

Execute the STOP instruction. The external circuitry shown in Figure 2 and Figure 3 will count the

number of bus cycles starting with the write to the low-power address and will stop the processor

clock on the first falling edge of the system clock after the bus cycle that reads the immediate data

of the STOP instruction. Figure 3 has one more flip-flop than Figure 2 because the MC68SEC000 in

µA for 3.3V operation and

Idd < 5

µA for 5.0V operation.

Figure 2. MC68SEC000 Low-Power Circuitry for 16-Bit Data Bus

D

Q

Q

CL

CK

D

Q

CK

D

Q

CK

ADDRESS_MATCH

AS

RESTART

RESET

CPU_CLK

SYSTEM_CLK

Q

Q

AS

CL

D

Q

Q

CL

CK

D

Q

Q

CL

CK

D

Q

Q

CK

ADDRESS_MATCH

RESTART

RESET

CPU_CLK

D

Q

Q

CL

CK

SYSTEM_CLK

AS

AS

AS