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PPC5643LFF0MMM8 Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc

Part # PPC5643LFF0MMM8
Description  MPC5643L Microcontroller Data Sheet
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

PPC5643LFF0MMM8 Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc

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MPC5643L Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Overview
Freescale Semiconductor
10
Programmable response for read-while-write sequences including support for stall-while-write, optional stall
notification interrupt, optional flash operation abort, and optional abort notification interrupt.
Separate and independent configurable access timing (on a per bank basis) to support use across a wide range of
platforms and frequencies.
Support of address-based read access timing for emulation of other memory types.
Support for reporting of single- and multi-bit error events.
Typical operating configuration loaded into programming model by system reset.
The platform flash controller is replicated for each processor.
1.3.8
Platform Static RAM Controller (SRAMC)
The SRAMC module is the platform RAM array controller, with integrated error detection and correction.
The main features of the SRAMC provide connectivity for the following interfaces:
XBAR Slave Port (64-bit data path)
ECSM (ECC Error Reporting, error injection and configuration)
•RAM array
The following functions are implemented:
ECC encoding (32-bit boundary for data and complete address bus)
ECC decoding (32-bit boundary and entire address)
Address translation from the AHB protocol on the XBAR to the RAM Array
The platform RAM controller is replicated for each processor.
1.3.9
Memory subsystem access time
Every memory access the CPU performs requires at least one system clock cycle for the data phase of the access. Slower
memories or peripherals may require additional data phase wait states. Additional data phase wait states may also occur if the
slave being accessed is not parked on the requesting master in the crossbar.
Table 2 shows the number of additional data phase wait states required for a range of memory accesses.
Table 2. Platform memory access time summary
AHB Transfer
Data Phase
Wait States
Description
e200z4d Instruction Fetch
TBD1
Flash prefetch buffer hit (page hit)
e200z4d Instruction Fetch
TBD
Flash prefetch buffer miss (at 120 MHz)
(based on 4-cycle random flash array access time)
e200z4d Data Read
TBD
RAM read
e200z4d Data Write
TBD
RAM 32-bit write
e200z4d Data Write
TBD
RAM 64-bit write (executed as 2 x 32-bit writes)
e200z4d Data Write
TBD
RAM 8-,16-bit write
(Read-modify-Write for ECC)
e200z4d Data Flash Read
TBD
Flash prefetch buffer hit (page hit)
e200z4d Data Flash Read
TBD
Flash prefetch buffer miss (includes 1-cycle of program flash
controller arbitration)


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