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MPC8379ECVRALGA Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc |
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MPC8379ECVRALGA Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc |
10 / 114 page MPC8379E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2 10 Freescale Semiconductor Power Characteristics 2.2 Power Sequencing The device requires its power rails to be applied in a specific sequence in order to ensure proper device operation. During the power ramp up, before the power supplies are stable and if the I/O voltages are supplied before the core voltage, there may be a period of time that all input and output pins will actively be driven and cause contention and excessive current. To avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core voltages (VDD and AVDD) before the I/O voltages and assert PORESET before the power supplies fully ramp up. VDD and AVDD must reach 90% of their nominal value before GVDD, LVDD, and OVDD reach 10% of their value, see Figure 3. I/O voltage supplies, GVDD, LVDD, and OVDD do not have any ordering requirements with respect to one another. Figure 3. Power-Up Sequencing Example Please note that the SerDes power supply (L[1,2]_nVDD) should follow the same timing as the core supply (VDD). The opposite sequence applies to the power down requirements. The I/O supplies must go down first and immediately followed by the core and PLL supplies. 3 Power Characteristics The estimated typical power dissipation for the MPC8379E device is shown in Table 5. Table 5. MPC8379E Power Dissipation 1 Core Frequency (MHz) CSB/DDR Frequency (MHz) Sleep Power at Tj =65°C (W) 2 Typical Application at Tj =65°C (W) 2 Typical Application at Tj =125°C (W) 3 Max Application at Tj =125°C (W) 4 333 333 1.45 1.9 3.2 3.8 167 1.45 1.8 3.0 3.6 400 400 1.45 2.0 3.3 4.0 266 1.45 1.9 3.1 3.8 t 90% V Core Voltage (VDD, AVDD) I/O Voltage (GVDD, LVDD, and OVDD) 0 0.7 V |
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