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PPC5643LFF0VMM8 Datasheet(PDF) 11 Page - Freescale Semiconductor, Inc |
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PPC5643LFF0VMM8 Datasheet(HTML) 11 Page - Freescale Semiconductor, Inc |
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11 / 98 page  Overview MPC5643L Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice Freescale Semiconductor 11 1.3.10 Error Correction Status Module (ECSM) The ECSM on this device manages the ECC configuration and reporting for the platform memories (flash memory and SRAM). It does not implement the actual ECC calculation. A detected error (double error for flash memory or SRAM) is also reported to the FCCU. The following errors and indications are reported into the ECSM dedicated registers: • ECC error status and configuration for flash memory and SRAM • ECC error reporting for flash memory • ECC error reporting for SRAM • ECC error injection for RAM 1.3.11 Peripheral bridge (PBRIDGE/AIPS-Lite) The peripheral bridge (referred to as PBRIDGE or AIPS-Lite throughout this document) implements the following features: • Duplicated periphery • Protocol translator bridge from AMBA to internal periphery interface (IPI) • Master access right per peripheral (per master: read access enable; write access enable) • Write buffering for peripherals • Checker applied on AIPS-Lite output toward periphery • Byte endianess swap capability 1.3.12 Interrupt Controller (INTC) The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems. For high-priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other. The INTC provides the following features: • Duplicated periphery • Unique 9-bit vector per interrupt source • 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source • Priority elevation for shared resource The INTC is replicated for each processor. e200z4d Peripheral Read TBD Peripheral Bridge read e200z4d Peripheral Write TBD Peripheral Bridge write NOTES: 1 To be determined Table 2. Platform memory access time summary (continued) AHB Transfer Data Phase Wait States Description |
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